Patents by Inventor Fred Gruner
Fred Gruner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10289469Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.Type: GrantFiled: October 28, 2016Date of Patent: May 14, 2019Assignee: Nvidia CorporationInventors: Nick Fortino, Fred Gruner, Ben Hertzberg
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Publication number: 20180121273Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventors: Nick Fortino, Fred Gruner, Ben Hertzberg
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Patent number: 9734545Abstract: One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number of clock cycles during which the graphics engine is idled. The function of the software method is performed by a firmware method that is executed by a processor within the GPU. The firmware method is executed to access and optionally update the state stored in the GPU. Unlike execution of a conventional software method, execution of the firmware method does not require an exchange of information between a CPU and the GPU. Therefore, the CPU is not interrupted and throughput of the CPU is not reduced.Type: GrantFiled: October 7, 2010Date of Patent: August 15, 2017Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., John Christopher Cook, Fred Gruner, Gregory Scott Palmer
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Patent number: 9490847Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.Type: GrantFiled: October 25, 2012Date of Patent: November 8, 2016Assignee: NVIDIA CorporationInventors: Fred Gruner, Shane Keil, John S. Montrym
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Patent number: 8321761Abstract: A memory module includes a plurality of register files. Each register file is associated with a set of error-correcting code (ECC) bits and ECC check/correct logic that can provide error-correcting functionality, if required. When error-correcting functionality is not required, ECC bits are grouped together to form additional register files, thereby providing additional storage space.Type: GrantFiled: September 28, 2009Date of Patent: November 27, 2012Assignee: NVIDIA CorporationInventors: Fred Gruner, Xiaogang Qiu, Yan Yan Tang
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Patent number: 8301980Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.Type: GrantFiled: September 28, 2009Date of Patent: October 30, 2012Assignee: NVIDIA CorporationInventors: Fred Gruner, Shane Keil, John S. Montrym
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Patent number: 8250439Abstract: A memory module includes a plurality of register files. Each register file is associated with a set of error-correcting code (ECC) bits and ECC check/correct logic that can provide error-correcting functionality, if required. When error-correcting functionality is not required, ECC bits are grouped together to form additional register files, thereby providing additional storage space.Type: GrantFiled: September 28, 2009Date of Patent: August 21, 2012Assignee: NVIDIA CorporationInventors: Fred Gruner, Xiaogang Qiu
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Patent number: 8190974Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.Type: GrantFiled: September 28, 2009Date of Patent: May 29, 2012Assignee: NVIDIA CorporationInventors: Fred Gruner, Shane Keil, John S. Montrym
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Publication number: 20110084972Abstract: One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number of clock cycles during which the graphics engine is idled. The function of the software method is performed by a firmware method that is executed by a processor within the GPU. The firmware method is executed to access and optionally update the state stored in the GPU. Unlike execution of a conventional software method, execution of the firmware method does not require an exchange of information between a CPU and the GPU. Therefore, the CPU is not interrupted and throughput of the CPU is not reduced.Type: ApplicationFiled: October 7, 2010Publication date: April 14, 2011Inventors: Jerome F. Duluk, JR., John Christopher Cook, Fred Gruner, Gregory Scott Palmer
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Publication number: 20110078537Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Inventors: FRED GRUNER, Shane KEIL, John S. MONTRYM
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Publication number: 20110078544Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Inventors: Fred GRUNER, Shane KEIL, John S. MONTRYM
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Patent number: 7813364Abstract: A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port aborts transmission of a data packet and waits a predetermined period of time to retransmit the data packet.Type: GrantFiled: December 11, 2006Date of Patent: October 12, 2010Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 7733905Abstract: A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination—creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets—providing the cross-bar switch with implicit multicast capability.Type: GrantFiled: February 1, 2007Date of Patent: June 8, 2010Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Publication number: 20070127469Abstract: A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination—creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets—providing the cross-bar switch with implicit multicast capability.Type: ApplicationFiled: February 1, 2007Publication date: June 7, 2007Applicant: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 7213129Abstract: A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.Type: GrantFiled: August 30, 1999Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Fred Gruner, Mike Morrison, Kushagra Vaid
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Publication number: 20070091880Abstract: A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port aborts transmission of a data packet and waits a predetermined period of time to retransmit the data packet.Type: ApplicationFiled: December 11, 2006Publication date: April 26, 2007Applicant: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 7170902Abstract: A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port aborts transmission of a data packet and waits a predetermined period of time to retransmit the data packet.Type: GrantFiled: December 21, 2001Date of Patent: January 30, 2007Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 7123585Abstract: Each sink port in a cross-bar switch provides for allocating bandwidth among data packets. Packets are assigned priority levels, and the cross-bar switch regulates bandwidth allocation for each priority level. A sink port records traffic volume for packet data of each priority level. The sink port calculates a weighted average bandwidth for each different priority level and determines whether to reject packet data for the priority level. When the packet data collected by a sink port exceeds a threshold, the sink port rejects data packets with priority levels having excessive weighted average bandwidths.Type: GrantFiled: December 21, 2001Date of Patent: October 17, 2006Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 7068603Abstract: A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination—creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets—providing the cross-bar switch with implicit multicast capability.Type: GrantFiled: July 6, 2001Date of Patent: June 27, 2006Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 6920529Abstract: A coprocessor transfers data between media access controllers and a set of cache memory without accessing main memory. The coprocessor includes a reception media access controller that receives data from a network and a transmission media access controller that transmits data to a network. A streaming output data transfer engine in the coprocessor transfers data from the reception media access controller to cache memory. A streaming input data transfer engine in the coprocessor transfers data from cache memory to the transmission media access controller. The coprocessor's data transfer engines transfer data between cache memory and the media access controllers in a single data transfer operation—eliminating the need to store data in an intermediary memory location between the cache memory and data transfer engines.Type: GrantFiled: March 25, 2002Date of Patent: July 19, 2005Assignee: Juniper Networks, Inc.Inventors: Fred Gruner, Robert Hathaway, Ricardo Ramirez