Patents by Inventor Fred Hause
Fred Hause has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8687417Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.Type: GrantFiled: October 5, 2007Date of Patent: April 1, 2014Inventors: Ruigang Li, Jingrong Zhou, David Donggang Wu, Zhonghai Shi, James F. Buller, Akif Sultan, Fred Hause, Donna Michael
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Patent number: 8564120Abstract: By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.Type: GrantFiled: December 21, 2009Date of Patent: October 22, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Anthony Mowry, David Farber, Fred Hause, Markus Lenski
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Patent number: 7804107Abstract: In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask.Type: GrantFiled: October 3, 2007Date of Patent: September 28, 2010Assignee: T-RAM Semiconductor, Inc.Inventors: Andrew E. Horch, Fred Hause
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Publication number: 20100164093Abstract: By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.Type: ApplicationFiled: December 21, 2009Publication date: July 1, 2010Inventors: Anthony Mowry, David Farber, Fred Hause, Markus Lenski
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Patent number: 7745337Abstract: A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.Type: GrantFiled: May 19, 2008Date of Patent: June 29, 2010Assignee: Globalfoundries Inc.Inventors: David G. Farber, Fred Hause, Markus Lenski, Anthony C. Mowry
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Patent number: 7741663Abstract: Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.Type: GrantFiled: October 24, 2008Date of Patent: June 22, 2010Assignee: Globalfoundries Inc.Inventors: Fred Hause, Anthony C. Mowry, David G. Farber, Markus E. Lenski
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Publication number: 20100102363Abstract: Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.Type: ApplicationFiled: October 24, 2008Publication date: April 29, 2010Applicant: Advanced Micro Devices, Inc.Inventors: Fred Hause, Anthony C. Mowry, David G. Farber, Markus E. Lenski
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Patent number: 7670932Abstract: MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.Type: GrantFiled: June 13, 2007Date of Patent: March 2, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Jianhong Zhu, Fred Hause, David Wu
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Publication number: 20090286389Abstract: A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.Type: ApplicationFiled: May 19, 2008Publication date: November 19, 2009Applicant: Advanced Micro Devices, Inc.Inventors: David G. Farber, Fred Hause, Markus Lenski, Anthony C. Mowry
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Publication number: 20090090969Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.Type: ApplicationFiled: October 5, 2007Publication date: April 9, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Ruigang Li, Jingrong Zhou, David Donggang Wu, Zhonghai Shi, James F. Buller, Mark W. Michael, Donna Michael, Akif Sultan, Fred Hause
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Publication number: 20080308879Abstract: MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Jianhong ZHU, Fred HAUSE, David WU
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Patent number: 7279367Abstract: In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask.Type: GrantFiled: December 7, 2004Date of Patent: October 9, 2007Assignee: T-Ram Semiconductor, Inc.Inventors: Andrew E. Horch, Fred Hause
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Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness
Patent number: 6967160Abstract: Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.Type: GrantFiled: January 26, 2005Date of Patent: November 22, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Eric Paton, Paul Raymond Besser, Simon S. Chan, Fred Hause -
Publication number: 20050101120Abstract: In a barrier formation process, an adhesion layer of refractory metal is deposited on sidewalls and bottom portions of a trench, and, subsequently, a nitride layer of the refractory metal is formed on the adhesion layer. After forming the nitride layer, the substrate is subjected to a heat treatment in a nitrogen-containing atmosphere to further convert residual refractory metal into nitride, thereby improving the barrier properties of the nitride layer in a subsequent process for filling in a contact metal, such as tungsten.Type: ApplicationFiled: March 27, 2003Publication date: May 12, 2005Inventors: Fred Hause, Gert Burbach, Volker Kahlert
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Patent number: 6888176Abstract: In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask.Type: GrantFiled: June 26, 2003Date of Patent: May 3, 2005Assignee: T-RAM, Inc.Inventors: Andrew E. Horch, Fred Hause
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Patent number: 6873051Abstract: Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.Type: GrantFiled: May 31, 2002Date of Patent: March 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Eric Paton, Paul Raymond Besser, Simon S. Chan, Fred Hause
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Patent number: 6255215Abstract: A process for forming a silicide layer using a metal layer formed by collimated deposition is provided. The collimated metal layer may, for example, be formed by sputtering metal particles and filtering the metal particles prior to forming the metal layer. By depositing metal in this manner, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. Lower silicidation reaction temperatures may also be employed.Type: GrantFiled: October 20, 1998Date of Patent: July 3, 2001Assignee: Advanced Micro ServicesInventors: Fred Hause, Charles E. May, William S. Brennan
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Process for breaking silicide stringers extending between silicide areas of different active regions
Patent number: 6242330Abstract: A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions.Type: GrantFiled: December 19, 1997Date of Patent: June 5, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Jon Cheek, Derick J. Wristers, Fred Hause -
Patent number: 6225168Abstract: Semiconductor devices having a metal gate electrode and a titanium or tantalum nitride gate dielectric barrier layer and processes for fabricating such devices are provided. The use of a metal gate electrode along with a titanium or tantalum nitride gate dielectric barrier layer can, for example, provide a highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.Type: GrantFiled: June 4, 1998Date of Patent: May 1, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Charles E. May, Fred Hause, Dim-Lee Kwong
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Patent number: 6159814Abstract: A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of implanting the gate material, usually a polysilicon, with a dopant ion that varies the level of oxide formation on the gate. The dopant ion is driven into undoped polysilicon. Nitrogen ions, may also be implanted in the polysilicon to contain the previously implanted ions. For N-type transistors, typically arsenic is implanted. For P-type transistors, typically boron is implanted. Gates are formed. The gate structure is then oxidized. The oxidation process is controlled to grow a desired thickness of silicon dioxide on the gate. The portion of the gate carrying the dopant grows silicon dioxide either more quickly or more slowly. An isotropic etch can then used to remove a portion of the silicon oxide and form a knob on each sidewall of the gate.Type: GrantFiled: November 12, 1997Date of Patent: December 12, 2000Assignee: Advanced, Micro Devices, Inc.Inventors: Mark Gardner, Fred Hause, Charles May