Patents by Inventor Fred Jaffin

Fred Jaffin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programming and/or erasing a memory device in response to its program and/or erase history
    Patent number: 7679961
    Abstract: For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: June Lee, Fred Jaffin
  • PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY
    Publication number: 20080266970
    Abstract: For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 30, 2008
    Inventors: June Lee, Fred Jaffin
  • Memory with row redundancy
    Patent number: 6469932
    Abstract: A flash memory device incorporating redundant rows. The memory device includes a memory array, control circuitry and a register. The control circuitry controls operations to the memory array. The register stores an address of a defect in the memory array and data indicating a type of defect associated with the address. The control circuitry increments row addresses during an erase operation based on the type of defect stored in the register.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: October 22, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Fred Jaffin, Abrahim Abedifard
  • MEMORY WITH ROW REDUNDANCY
    Publication number: 20020126529
    Abstract: A flash memory device incorporating redundant rows. The memory device includes a memory array, control circuitry and a register. The control circuitry controls operations to the memory array. The register stores an address of a defect in the memory array and data indicating a type of defect associated with the address. The control circuitry increments row addresses during an erase operation based on the type of defect stored in the register.
    Type: Application
    Filed: March 12, 2001
    Publication date: September 12, 2002
    Applicant: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Fred Jaffin, Ebrahim Abedifard