Patents by Inventor Fred Jenne

Fred Jenne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6818558
    Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 16, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Manuj Rathor, Krishnaswamy Ramkumar, Fred Jenne, Loren Lancaster
  • Patent number: 6709928
    Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed in which a SONOS-type dielectric may include a charge storing dielectric (206) that includes at least one charge trapping dielectric layer (212) formed within. A charge trapping dielectric layer (212) may be a silicon-rich silicon nitride layer that may trap charge that could otherwise tunnel through a charge storing dielectric (206). A method may include forming a tunneling dielectric (302), forming a first portion of a charge storing layer (304-0), forming a charge trapping layer (306), forming a second portion of a charge storing layer (304-1), and forming a top dielectric (308).
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: March 23, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fred Jenne, Loren Thomas Lancaster
  • Patent number: 6172907
    Abstract: According to one embodiment, a nonvolatile storage circuit (100) can include a volatile portion (102) that includes p-channel metal-oxide-semiconductor (MOS) transistors (106-0 and 106-1) and n-channel MOS (NMOS) transistors (108-0 and 108-1) arranged in a complementary MOS (CMOS) latch configuration. Also included are nonvolatile devices (116-0 and 116-1) disposed between PMOS transistor 106-0 and NMOS transistor 108-0, and between PMOS transistor 106-1 and NMOS transistor 108-1. Nonvolatile devices (116-0 and 116-1) can include silicon-oxide-nitride-semiconductor (SONOS) transistors that can be programmed to opposite states to recall a logic value when power is applied to the nonvolatile storage circuit (100). In a read mode, a bias voltage VBIAS can be applied to nonvolatile devices (116-0 and 116-1) that tends to retain charge in both nonvolatile devices (116-0 and 116-1).
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: January 9, 2001
    Assignee: Cypress Semiconductor Corporation
    Inventor: Fred Jenne