Abstract: A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA) circuitry. The design structure limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.

Abstract: A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.

Abstract: A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.

Abstract: A method of testing a first memory such as a RAM having data storage at a plurality of individually addressable storage locations is provided. A portion of the address for the addressable locations of the first memory is supplied as an output from a second memory such as a CAM. The second memory includes a decoder to provide a decoded address as input signals to the second memory. During the testing, first memory specific addresses are provided to the decoder as input. These first memory specific addresses are decoded by the decoder and are gated as input signals to address the first memory. In this way, the decoder which in normal operation provides decoded input signals to the CAM is used to provide input signals to the RAM, thus obviating the need for any scan chain latches surrounding the RAM. This enables conventional testing apparatus to provide the necessary test protocol for the RAM through the decoder normally used by the CAM.