Patents by Inventor Fred L. Yang

Fred L. Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for reducing RC parasitics in interconnect networks of an integrated circuit
    Patent number: 6763504
    Abstract: A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Vasant B. Rao, Ravichander Ledalla, Jeffrey P. Soreff, Fred L. Yang
  • Method for reducing RC parasitics in interconnect networks of an integrated circuit
    Publication number: 20040049746
    Abstract: A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Applicant: International Business Machine Corporation
    Inventors: Vasant B. Rao, Ravichander Ledalla, Jeffrey P. Soreff, Fred L. Yang