Patents by Inventor Fred Liao

Fred Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7999819
    Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: August 16, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Fred Liao, Yijung Su, Yiping Chen, Mark Zheng
  • Patent number: 7876329
    Abstract: Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: January 25, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Fred Liao, Yijung Su, Yiping Chen, Mark Zheng
  • Patent number: 7551176
    Abstract: Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: June 23, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Fred Liao, John Brothers
  • Publication number: 20090128575
    Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Fred Liao, Yijung Su, Yiping Chen, Mark Zheng
  • Publication number: 20090066714
    Abstract: Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 12, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Fred Liao, Yijung Su, Yiping Chen, Mark Zheng
  • Publication number: 20080049031
    Abstract: Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.
    Type: Application
    Filed: August 24, 2006
    Publication date: February 28, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Fred Liao, John Brothers
  • Patent number: 7218317
    Abstract: Z buffer traffic experienced during graphics processing is reduced by using a compression mechanism to reduce the amount of information stored in the z buffer. The compression mechanism may be a delta-based z compression mechanism, which stores deltas in the z buffer rather than actual z values. These deltas may be used at a later time to compute the z values. By storing deltas instead of actual z values, the compression mechanism makes it possible to store significantly less information in the z buffer. By reducing the amount of information stored in the z buffer, less information will be read from and written to the z buffer, which in turn, reduces z buffer traffic. To further reduce z buffer traffic, selected deltas may be stored not in the z buffer but rather in a storage local to a graphics processing mechanism (GPM). Storing selected deltas in local storage obviates the need to read from or write to the z buffer for those deltas. As a result, z buffer traffic is even further reduced.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: May 15, 2007
    Assignee: Via Technologies, Inc.
    Inventors: Fred Liao, Michael Hong
  • Patent number: 7126615
    Abstract: Systems and methods are provided for compressing computer graphics color data in a system utilizing a multi-sample anti-aliasing scheme using multiple planes for storing color data samples. Each of the planes is configured as a block of contiguous memory.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 24, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: Fred Liao
  • Publication number: 20060103658
    Abstract: Systems and methods are provided for compressing computer graphics color data in a system utilizing a multi-sample anti-aliasing scheme using multiple planes for storing color data samples. Each of the planes is configured as a block of contiguous memory.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Inventor: Fred Liao
  • Publication number: 20050057564
    Abstract: Z buffer traffic experienced during graphics processing is reduced by using a compression mechanism to reduce the amount of information stored in the z buffer. The compression mechanism may be a delta-based z compression mechanism, which stores deltas in the z buffer rather than actual z values. These deltas may be used at a later time to compute the z values. By storing deltas instead of actual z values, the compression mechanism makes it possible to store significantly less information in the z buffer. By reducing the amount of information stored in the z buffer, less information will be read from and written to the z buffer, which in turn, reduces z buffer traffic. To further reduce z buffer traffic, selected deltas may be stored not in the z buffer but rather in a storage local to a graphics processing mechanism (GPM). Storing selected deltas in local storage obviates the need to read from or write to the z buffer for those deltas. As a result, z buffer traffic is even further reduced.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 17, 2005
    Inventors: Fred Liao, Michael Hong
  • Patent number: 6476808
    Abstract: A token-based buffer system for a geometry pipeline in three-dimensional graphics comprises: a buffer control initialization (BCI) unit, a new token or index module, a geometry control pipeline, a vertex buffer, and a processing engine. The token-based buffer system provides a shared resource environment in which tokens are assigned for blocks of data. Each block of data includes that data necessary for each unit or stage in the geometry pipeline to perform its computation. The use of tokens is advantageous because it optimizes the storage efficiency for storing the blocks of data and ensures the correctness of the data as it is passed between stages.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: November 5, 2002
    Assignee: S3 Graphics Co., Ltd.
    Inventors: Dong-Ying Kuo, Mike Hong, Fred Liao
  • Patent number: 6304268
    Abstract: A trilinear texture filtering system and method that improves the locality of texture map accesses in a multum in parvo (MIP) map so as to reduce page breaks and provide improved performance. The present invention includes a texture cache having a unique addressing and accessing scheme that allows localized reads of the texture map from each of four banks in the texture cache. This is coupled with a unique texture-mapping unit that includes a first level generator, a second level generator and an interpolator. In generating the lower-resolution texture map version, the present invention filters neighboring texels from the higher-resolution version. Thus, an n×n (e.g. 2×2) square of texels at the higher-resolution level is reduced to a single texel at the lower-resolution level. This technique permits the lower-resolution level to be derived without requiring additional read operations from texture memory with potentially poor locality.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: October 16, 2001
    Assignee: S3 Graphics Co., Ltd.
    Inventors: Konstantine I Iourcha, Fred Liao, Michael Hong