Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon.

Abstract: The method as disclosed reduces the topological step between the uppermost surface of a substrate and the uppermost surface of a shallow trench isolation feature. The method includes the steps of forming a pad oxide layer overlying a substrate, forming a stop layer overlying the pad oxide layer, forming a second oxide layer overlying the stop layer, forming a patterning layer overlying the second oxide layer, and patterning the patterning layer and underlying stack to form an exposed portion of the substrate. The exposed portion of substrate is etched to form a trench, and the remaining portion of the oxidation resistant layer is removed. Further, a dielectric layer is formed overlying the remaining portion of the second oxide layer, and filling the trench. A portion of the dielectric layer is removed to leave the top of the dielectric layer substantially level with the stop layer, and then the stop layer is removed.

Abstract: A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

Abstract: A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region.

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa.

Abstract: A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.

Abstract: The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa.

Abstract: An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature needed to repair implant damage and activate the LDD dopants. High pressure indoctrination of nitrogen is believed to provide the same amount of lattice repair and activation achieved if anneal temperatures were substantially higher.

Abstract: A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner.

Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

Abstract: A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate. In an embodiment, a polysilicon gate conductor is provided which is arranged between a pair of opposed sidewall surfaces upon a gate dielectric. The gate dielectric is arranged upon a semiconductor substrate. Nitride is deposited from a high density plasma source across exposed surfaces of the substrate and the gate conductor. The high density plasma source may be generated within an ECR or ICP reactor containing a gas bearing N2 and SiH4. The energy and flux of electrons, ions, and radicals within the plasma are strictly controlled by the magnetic field such that a substantially stoichiometric and contaminant-free nitride is deposited upon the semiconductor topography. Thereafter, the nitride is anisotropically etched so as to form nitride spacers laterally adjacent the sidewall surfaces of the gate conductor.

Abstract: A method of making a MOS transistors in an integrated circuit includes forming a plurality of doped source and drain regions adjacent respective gate structures that include gate dielectrics, gate conductors and spacers. The plurality of doped source and drain regions are formed at different depths, at different doses and with differing dopants. In one embodiment, first doped source and drain regions are formed at a first depth, at a first dose using a first dopant while second doped source and drain regions are formed at a second depth, at a second dose using a second dopant. The first depth is shallower than the second depth so that the first doped source and drain regions serve as sacrificial doped regions that are consumed in a silicidation process when they are converted into a silicide by being combined with a silicidation metal. However, the second doped source and drain regions maintain their doping profiles and dopant levels.

Abstract: A semiconductor process in which a first silicide is formed on silicon upper surfaces upon which a second silicide is selectively deposited. A refractory metal is blanket deposited on a semiconductor substrate. The semiconductor substrate is then heated to a first temperature to react portions of the refractory metal above the exposed silicon surfaces to form a first phase of a first silicide. The unreacted portions of the refractory metal then remove, typically with a wet etch process. The semiconductor substrate is then heated to a second temperature to form a second phase of the first silicide. The second temperature is typically greater than the first, and the resistivity of the second phase is less than a resistivity of the first phase. Thereafter, a second metal silicide is selectively deposited on the first silicide, preferably through the use of a chemical vapor deposition process.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract: A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.