Patents by Inventor Fred Reece Clayton

Fred Reece Clayton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197829
    Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Congyong Zhu, Anthony Ciancio, Fred Reece Clayton, Lawrence Scott Klingbeil, Bernhard Grote
  • Patent number: 11450616
    Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 20, 2022
    Assignee: NXP USA, INC.
    Inventors: David Robert Currier, Darrell Glenn Hill, Fred Reece Clayton, Alan J. Magnus, Warren Crapse
  • Patent number: 11437301
    Abstract: A device includes a substrate, an insulating layer that includes an etch stop layer formed over an upper surface of the substrate, a first conductive region formed over the insulating layer, and an opening formed within the substrate that extends from a lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region. A method for forming the device includes forming the substrate, forming the insulating layer that includes the etch stop layer over the upper surface of the substrate, forming a first conductive region over the insulating layer; and forming an opening within the substrate that extends from the lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region formed over the insulating layer.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: September 6, 2022
    Assignee: NXP USA, Inc.
    Inventors: Yuanzheng Yue, James Allen Teplik, Bruce McRae Green, Fred Reece Clayton
  • Publication number: 20220122903
    Abstract: A device includes a substrate, an insulating layer that includes an etch stop layer formed over an upper surface of the substrate, a first conductive region formed over the insulating layer, and an opening formed within the substrate that extends from a lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region. A method for forming the device includes forming the substrate, forming the insulating layer that includes the etch stop layer over the upper surface of the substrate, forming a first conductive region over the insulating layer; and forming an opening within the substrate that extends from the lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region formed over the insulating layer.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 21, 2022
    Inventors: Yuanzheng Yue, James Allen Teplik, Bruce McRae Green, Fred Reece Clayton
  • Publication number: 20220037264
    Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Applicant: NXP USA, Inc.
    Inventors: David Robert Currier, Darrell Glenn Hill, Fred Reece Clayton, Alan J. Magnus, Warren Crapse