Abstract: A Complementary CMOS differential amplifier has automatic operating point adjustment (self-biasing) and the properties of a rail-to-rail amplifier. The CMOS differential amplifier uses folded cascodes and is considerably faster in operation than previous CMOS differential amplifiers, since it comprises a circuit element that ensures that, during the operation of the CMOS differential amplifier, all MOS FETs of the cascodes operate in their saturation range (that is not in their resistive range). The CMOS differential amplifier may be used in an input stage, a signal distribution circuit and a clock pulse distribution circuit.

Abstract: A Complementary CMOS differential amplifier has automatic operating point adjustment (self-biasing) and the properties of a rail-to-rail amplifier. The CMOS differential amplifier uses folded cascodes and is considerably faster in operation than previous CMOS differential amplifiers, since it comprises a circuit element that ensures that, during the operation of the CMOS differential amplifier, all MOS FETs of the cascodes operate in their saturation range (that is not in their resistive range). The CMOS differential amplifier may be used in an input stage, a signal distribution circuit and a clock pulse distribution circuit.

Abstract: The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time.

Abstract: The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time.

Abstract: A method and apparatus for performing adaptive differential pulse code modulation. The method and apparatus is particularly adapted for compliance with the ITU-T G.726 international standard. Certain intermediate values, including Y and SE, needed to compress or decompress a given sample are pre-calculated prior to receipt of the actual sample to which they correspond. Accordingly, when the sample is received, intermediate variables Y and SE are essentially immediately available. This allows the output value SR (during a decompression cycle) or I (during a compression cycle) to be available one clock cycle after receipt of a sample. The remaining clock cycles corresponding to that sample period are used to precalculate the intermediate variables Y and SE for the next sample. The method and apparatus requires only fifteen clock cycles per conversion.