Abstract: A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

Abstract: A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted (52) to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (54). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths (56) to derive second modified versions of the designs (58). These second modified versions are compared with each other (60) to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit 62, or otherwise further evaluated.

Abstract: A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted (52) to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (54). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths (56) to derive second modified versions of the designs (58). These second modified versions are compared with each other (60) to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit 62, or otherwise further evaluated.