Abstract: Techniques for a write-once-read-many caching are described. In an embodiment, an apparatus includes a first physical register in a first cluster of a clustered processor core, the first physical register to store a write-once-read-many (WORM) value; a first WORM cache in the first cluster of the clustered processor core, the first WORM cache to store the WORM value to be read without reading the WORM value from the first physical register; a second physical register in a second cluster of the clustered processor core; and a second WORM cache in the second cluster of the clustered processor core, wherein, in connection with an intercluster MOV operation, the WORM value from the first WORM cache is stored in the second WORM cache and the second physical register.

Abstract: Techniques for dead producer elimination are described. In an embodiment, an apparatus includes micro-operation (uop) fusion circuitry to analyze a line of uops to find a producer uop and a consumer uop meeting fusibility criteria and to morph the consumer uop into a fused uop, wherein the line of uops includes a number of uops corresponding to a maximum number of uops that can be allocated in a single cycle; dead producer elimination (DPE) circuitry to determine that DPE conditions are satisfied; and an arithmetic-logic unit to execute the fused uop without the producer uop having been executed.

Abstract: Techniques and mechanisms for communicating information between clusters of a processor. In an embodiment, a processor core comprises circuitry to identify a condition wherein a first micro-operation (uop) of a uop sequence is to produce a value of an operand, a second uop of the uop sequence is to use the value of the operand, and different respective clusters of processor resources are to execute the first uop and the second uop. Based on the condition, the processor core supplements a strand of uops with a cross-cluster communication uop, wherein the strand comprises one of the first uop or the second uop. In another embodiment, one of the clusters executes the cross-cluster communication uop to provide a value of the operand to another cluster via a cross-cluster network.

Abstract: Techniques and mechanisms for a cache structure to facilitate time-efficient (re)use of an operand value in the execution of a micro-operation (?op). In an embodiment, a processor comprises a physical register file (PRF), and a cache which is coupled between a writeback path and the PRF. The cache functions as a holding buffer that stores operand values recently provided via one or more ports of the processor. A given operand value is available to be accessed in the cache for use in executing a ?op. The operand value is subject to being drained into the PRF, from which it can then be accessed for use in the ?op execution. In another embodiment, a reservation station is configured to track a readiness state of the ?op based on information which specifies that the cache is a currently a repository of the operand value.

Abstract: Techniques for per allocation cycle micro-operation fusion are described. In an embodiment, an apparatus includes micro-operation (uop) fusion circuitry and an arithmetic-logic unit (ALU). The uop fusion circuitry is to analyze a line of uops to find a producer uop and a consumer uop meeting fusibility criteria and to morph the consumer uop into a fused uop, wherein the line of uops includes a number of uops corresponding to maximum number of uops that can be allocated in a single cycle. The ALU is to execute the fused uop.

Abstract: An apparatus and method for hard-partitioned threading in a clustered processor core. For example, one embodiment of a processor comprises: front end circuitry to fetch instructions of a number of software threads from a memory; out-of-order execution circuitry comprising a set of partitionable execution resources to execute the instructions; and circuitry to dynamically allocate the set of partitionable execution resources to a plurality of hardware threads, wherein a different isolated subset of the partitionable execution resources are allocated to each hardware thread based, at least in part, on characteristics of each respective software thread and the number of software threads.

Abstract: A system for aligning a rotating output shaft of a gas turbine with a rotating input shaft of a gearbox is disclosed. A turbine-side assembly has a first body configured to be attached to the casing of an engine and a rotatable alignment tool attached thereto. A gearbox-side assembly has a second body configured to be attached to the input power coupling of a gearbox and a rotatable second alignment tool attached thereto. The first alignment tool and second alignment tool are not physically coupled to one another, however, are configured to functionally communicate with each other to indicate when an output shaft and input shaft are aligned.

Abstract: A global positioning system (GPS) tracking device that includes a casing including a GPS transmitting and receiving unit configured to transmit and receive GPS signals including GPS routing information; a signal amplifying unit coupled with the GPS transmitting and receiving unit and configured to amplify cell signals; and a timing unit configured to receive power from an external power supply unit and to control power supply to the GPS transmitting and receiving unit and the signal amplifying unit for a predetermined time period