Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.

Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.

Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.

Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.

Abstract: A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.

Abstract: A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.

Abstract: The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits.

Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.

Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.

Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.

Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.

Abstract: A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance.

Abstract: A method and a circuit for detecting a disturbance of a state of at least one first flip-flop from a group of several first flip-flops of an electronic circuit, wherein: the respective outputs of the first flip-flops in the group are, independently from their functional purpose, combined to provide a signal and its inverse, triggering two second flip-flops having data inputs forced to a same state, the respective outputs of the second flip-flops being combined to provide the result of the detection; and a pulse signal comprising a pulse at least for each triggering edge of one of the first flip-flops in the group initializes the second flip-flops.

Abstract: The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits.

Abstract: An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.

Abstract: An electronic circuit includes a logic circuit formed from a plurality of logic units. The electronic circuit also includes a plurality of memory units capable of forming a shift register, capable of being connected to the logic units, and having terminals for reception of command signals to write data into the logic units and to read data from the logic units. The electronic circuit further includes an access controller having a plurality of outputs connected to the terminals of the memory units and capable of applying the command signals to the outputs. In addition, the electronic circuit includes a scrutinizing module capable of a plurality of functions.

Abstract: An electronic circuit containing a processing unit for executing program instructions, including at least one unit for recognizing at least one first instruction operator in the program and for converting this first operator into another instruction operator, both operators being interpretable by the processing unit. A method for controlling the access to data by such a circuit.

Abstract: A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result of the AND logic function applied to the logic signals of the group of logic signals. The value of the control word is monitored as it propagates in the shift register, and a synchronization error signal is sent if the control word changes value. Application in particular for checking the integrity of a clock tree in an integrated circuit.