Abstract: A near-field communication (NFC) receiver includes first and second input terminals for receiving first and second input signals having a modulated signal portion and a carrier signal portion. The receiver includes a digital-to-analog converter (DAC), a mixer, a track-and-hold (T&H) circuit, an amplifier, and an analog-to-digital converter. The mixer has a first input coupled to receive the first and second input signals and a second input coupled to receive a low frequency current from the DAC. The mixer subtracts the carrier portion from the first and second input signals using the DAC current at a level determined using a DSP in a feedback loop to approximate the carrier. The T&H circuit has an input coupled to receive the combined current and an output to provide a series of output samples. The ADC is coupled to receive the amplified output signal and to provide a digital representation of the amplified output signal.

Abstract: A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.

Abstract: A near-field communication (NFC) receiver includes first and second input terminals for receiving first and second input signals having a modulated signal portion and a carrier signal portion. The receiver includes a digital-to-analog converter (DAC), a mixer, a track-and-hold (T&H) circuit, an amplifier, and an analog-to-digital converter. The mixer has a first input coupled to receive the first and second input signals and a second input coupled to receive a low frequency current from the DAC. The mixer subtracts the carrier portion from the first and second input signals using the DAC current at a level determined using a DSP in a feedback loop to approximate the carrier. The T&H circuit has an input coupled to receive the combined current and an output to provide a series of output samples. The ADC is coupled to receive the amplified output signal and to provide a digital representation of the amplified output signal.

Abstract: Embodiments are provided for a method of operating a receiver system, the receiver system comprising one or more channels, the method comprising: monitoring a residual DC (direct current) offset in a present channel by sampling an output of an analog-to-digital converter (ADC) of the present channel; adjusting a DCO (direct current offset) correction signal that corresponds to the residual DC offset in response to an absolute value of the residual DC offset exceeding a programmable DCO threshold; and subtracting the DCO correction signal from an analog signal provided to the ADC to reduce the residual DC offset below the programmable DCO threshold.

Abstract: Embodiments are provided for a method of operating a receiver system, the receiver system comprising one or more channels, the method comprising: monitoring a residual DC (direct current) offset in a present channel by sampling an output of an analog-to-digital converter (ADC) of the present channel; adjusting a DCO (direct current offset) correction signal that corresponds to the residual DC offset in response to an absolute value of the residual DC offset exceeding a programmable DCO threshold; and subtracting the DCO correction signal from an analog signal provided to the ADC to reduce the residual DC offset below the programmable DCO threshold.

Abstract: The present invention relates to the field of wireless communication systems and in particular to an apparatus and a method for detecting preambles according to IEEE 802.11a/b/g wireless LAN standards and its application to an 802.11 multimode receiver. The proposed apparatus is capable of detecting 802.11a/b/g preambles by using two auxiliary low-resolution ADCs (down to 1 bit) coupled with a preamble detector. The purpose of this apparatus which is located within the RF section of the receiver upstream of the baseband section, is to offload or discharge the baseband functions by performing a signal discrimination and waking up the baseband functions only if the received signal is determined to embed either an 802.11a/g or 802.11b preamble. This results in significant power savings in a multimode 802.

Abstract: A system for estimating the bandwidth of a baseband filter that produces a phase shift on arriving analog signals is disclosed. The system comprises means for generating a digital reference clock signal and means for converting the digital reference clock signal into an analog reference clock signal to be input to the baseband filter. Phase comparison means are coupled to the baseband filter for comparing the digital reference clock signal to the analog reference clock signal phase shifted through the baseband filter. A digital pulsed signal that is representative of the phase shift is generated, and digital circuit means connected to the phase comparison means convert the digital pulsed signal into a digital value, the digital value being proportional to the phase shift of the baseband filter.

Abstract: A system for estimating the bandwidth of a baseband filter that produces a phase shift on arriving analog signals is disclosed. The system comprises means for generating a digital reference clock signal and means for converting the digital reference clock signal into an analog reference clock signal to be input to the baseband filter. Phase comparison means are coupled to the baseband filter for comparing the digital reference clock signal to the analog reference clock signal phase shifted through the baseband filter. A digital pulsed signal that is representative of the phase shift is generated, and digital circuit means connected to the phase comparison means convert the digital pulsed signal into a digital value, the digital value being proportional to the phase shift of the baseband filter.