Abstract: A register renaming unit 8 has mapping control circuitry 24 which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system 2. One example of circumstances which can be detected from the current state and in which mapping can be suppressed and the existing mapping reused are that in respect of the existing physically mapped register there are no pending writes, no pending reads and no pending requirement for that physically mapped register to be preserved as a recovery register. Another example of a current state in which a mapping can be reused is adjacent program instructions having mutually exclusive condition codes and sharing a destination register such that only one of those adjacent instructions will every be executed.

Abstract: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.

Abstract: The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for processing instructions of said instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said register renaming circuitry comprising: a first data store for storing a future renaming table, said future renaming table comprising renaming values for mapping registers from said architectural set of registers to registers in said physical set of registers for instructions that are to be executed or are currently being executed by said processor; a second da

Abstract: A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster.

Abstract: A data processing system 2 utilises a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanism 10, 26 includes a renaming recovery unit 26 which enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt.

Abstract: Apparatus for processing data under control of data processing instructions specifying data processing operations, said apparatus comprising: a first execution mechanism operable to execute a first set of data processing instructions; a second execution mechanism operable to execute a second set of data processing instructions, said first set of data processing instructions overlapping with said second set of data processing instructions such that one or more data processing instructions are executable by either said first execution mechanism or said second execution mechanism; and an execution mechanism selector operable to pseudo randomly selected either said first execution mechanism or said second execution mechanism to execute one or more data processing instructions that are executable by either said first execution mechanism or said second execution mechanism.

Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.