Patents by Inventor Frederic Darthenay
Frederic Darthenay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250138564Abstract: A voltage regulator utilizes an external pass transistor coupled between a supply voltage node and a regulated node. The voltage regulator includes an internal pass transistor that is coupled between the supply voltage node and the regulated node. A two-tap voltage divider between the regulated node and a ground node provides two feedback voltages. A first control loop that controls the external pass transistor receives the first feedback voltage and a second control loop that controls the internal pass transistor receives the second feedback voltage. At startup the control loops run concurrently but the first control loop is prioritized to reduce load current provided by the internal pass transistor at the end of startup. The voltage difference between the first and second feedback voltages ensures prioritization of the first control loop and the external pass transistor supplies most or all of the load current.Type: ApplicationFiled: October 14, 2024Publication date: May 1, 2025Inventors: Vincent Geffroy, Jean-Robert Tourret, Franck Goussin, Frederic Darthenay
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Publication number: 20250036238Abstract: A method for display noise canceling in a touch sensing system includes measuring a first feedback voltage of a feedback node resistively coupled to a line voltage of a capacitive touch panel, the line voltage formed by a continuous wave output of an amplifier responsive to a reference voltage difference between the first feedback voltage and a reference voltage. A second feedback voltage is clamped to a first upper voltage threshold in response to a first voltage difference between the first feedback voltage and the reference voltage being greater than the first upper voltage threshold. The second feedback voltage is clamped to a first lower voltage threshold in response to the first voltage difference being less than the first lower voltage threshold.Type: ApplicationFiled: July 5, 2024Publication date: January 30, 2025Inventors: Jean-Robert Tourret, Franck Goussin, Frederic Darthenay, Vincent Geffroy
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Publication number: 20240393910Abstract: A touch screen is disclosed having a length and a height, and comprising interspaced and galvanically isolated first and second arrays of touch pads; wherein the first array of touch pads comprises a plurality of first strings of series-connected touch pads, each first string forming a drive line and extending in a first general direction; wherein the second array of touch pads comprises a plurality of second strings of series-connected touch pads, each second string forming a read line and extending in a second general direction, different to said first general direction; wherein the first general direction and the second general direction are each different from the length direction; and wherein the touch screen is configured for capacitive-based sensing which may be based on a change in a mutual capacitance between individual ones of the drive lines and individual ones of the read lines.Type: ApplicationFiled: May 14, 2024Publication date: November 28, 2024Inventors: Frederic Darthenay, Jean-Robert Tourret, Franck Goussin, Vincent Geffroy
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Publication number: 20240380372Abstract: An amplifier circuit comprising: a first-stage residue-reduction storage unit; a final-stage residue-reduction storage unit; and a switching network. The switching network is operable to control the amplifier circuit according to the following operational configurations: a first residue-reduction configuration; a second residue-reduction configuration; and an operational configuration. Such an amplifier circuit uses a low number of residue-reduction steps to reduce global residual voltage to a very low level when the amplifier circuit is subsequently used in the operational configuration.Type: ApplicationFiled: May 6, 2024Publication date: November 14, 2024Inventor: Frederic Darthenay
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Publication number: 20240302918Abstract: A touch panel system that includes drivers for providing detection signals on a first plurality of electrodes of a touch panel where each detection signal includes one or more frequency signal components with each frequency signal component having a frequency and a phase offset. The detection signals includes at least three phase offsets for at least one frequency of the frequency signal components. Each detection signal has a unique frequency-phase offset combination of the one or more frequency signal components. The unique combinations allow for the determination of a touch at specific locations on the panel by sensing signals on a second set of electrodes.Type: ApplicationFiled: February 26, 2024Publication date: September 12, 2024Inventors: Franck Goussin, Frederic Darthenay, Jean-Robert Tourret, Vincent Geffroy
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Publication number: 20240302915Abstract: A touch panel includes a first plurality of electrodes and a second plurality of electrodes. A plurality of transmitters generate a plurality of transmit signals by modulating a common sine wave signal with a set of orthogonal modulation signals, and drive each transmit signal onto a corresponding electrode of the first plurality of electrodes. Each transmit signal is generated by modulating the common sine wave signal with a unique orthogonal modulation signal of the set of orthogonal modulation signals. At least two of the plurality of transmit signals are not orthogonal. Each receiver of a plurality of receivers senses a receive signal on a corresponding electrode of the second plurality of electrodes and generates a set of correlation signals by correlating the receive signal with each transmit signal of the plurality of transmit signals. The sets of correlation signals are used to detect a touch event on the touch panel.Type: ApplicationFiled: March 5, 2024Publication date: September 12, 2024Inventors: Frederic Darthenay, Jean-Robert Tourret, Franck Goussin, Vincent Geffroy
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Publication number: 20240126311Abstract: Systems and methods for providing voltage regulators with sliced pole tracking are discussed. In some embodiments, a voltage regulator may include: an error amplifier, a voltage-to-current converter coupled to the error amplifier, and a current-to-current converter coupled to the voltage-to-current converter, where the current-to-current converter comprises a sliced pole tracking circuit coupled to a power device, and where the power device is configured to provide an output voltage to a load.Type: ApplicationFiled: October 11, 2023Publication date: April 18, 2024Inventor: Frederic Darthenay
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Publication number: 20230091838Abstract: A receiver path circuit includes a first stage, a down-sampler and a second stage. The first stage is configured to filter a mixer-output-signal received from a mixer and provide a first-stage-output-signal. The down-sampler is configured to down-sample the first-stage-output-signal to provide a transition-signal having a transition-frequency. The transition-frequency is lower than the frequency of the first-stage-output-signal. The second stage includes a switched-capacitor circuit that is configured to filter and reduce the frequency of the transition-signal in order to provide a second-stage-output-signal to an ADC.Type: ApplicationFiled: August 31, 2022Publication date: March 23, 2023Inventors: Frederic Darthenay, Khurram Waheed
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Patent number: 10763877Abstract: An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.Type: GrantFiled: May 29, 2019Date of Patent: September 1, 2020Assignee: NXP B.V.Inventor: Frederic Darthenay
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Publication number: 20190379387Abstract: We disclose an apparatus for determining one or more calibration values of an ADC, the apparatus configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal comprising the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal comprising the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal, the apparatus configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.Type: ApplicationFiled: May 29, 2019Publication date: December 12, 2019Inventor: Frederic Darthenay
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Patent number: 9166842Abstract: RF repeater circuits may be used to regenerate an RF signal. A method and apparatus is described for regenerating a received RF signal the RF signal comprising a plurality of channels, each channel comprising a plurality of channel symbols, the method comprising producing a digitized RF signal from the received RF signal, extracting spectral information of each of the channels from the digitized RF signal, recovering one or more channel symbols from each of the plurality of channels, remodulating the channel symbols, and converting the remodulated channel symbols to an analog signal resulting in a regenerated RF signal.Type: GrantFiled: December 19, 2013Date of Patent: October 20, 2015Assignee: NXP, B.V.Inventor: Frederic Darthenay
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Publication number: 20150180687Abstract: RF repeater circuits may be used to regenerate an RF signal. A method and apparatus is described for regenerating a received RF signal the RF signal comprising a plurality of channels, each channel comprising a plurality of channel symbols, the method comprising producing a digitized RF signal from the received RF signal, extracting spectral information of each of the channels from the digitized RF signal, recovering one or more channel symbols from each of the plurality of channels, remodulating the channel symbols, and converting the remodulated channel symbols to an analog signal resulting in a regenerated RF signal.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: NXP B.V.Inventor: Frederic Darthenay
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Patent number: 8830095Abstract: A track and hold circuit has a main transistor for which the gate voltage is provided by a buffer circuit which is supplied with a different voltage supply than the circuit of the main transistor. This avoids the need for a bootstrap circuit.Type: GrantFiled: February 19, 2013Date of Patent: September 9, 2014Assignee: NXP, B.V.Inventor: Frederic Darthenay
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Publication number: 20110032648Abstract: An electrostatic discharge protection structure (200) for an integrated circuit, the electrostatic discharge protection structure (200) comprising: a first silicon controlled rectifier structure (211) having a first triggering voltage, the first rectifier structure (211) being directly connected to an input (250) of the electrostatic discharge protection structure (200); a second silicon controlled rectifier structure (222) having a second triggering voltage lower than the first triggering voltage, the second rectifier structure (222) being connected to the input (250) via a resistor (221); and a secondary over-voltage protection unit (231) connected to the input (250) via the resistor (221).Type: ApplicationFiled: March 3, 2009Publication date: February 10, 2011Applicant: NXP B.V.Inventors: Frederic Darthenay, Taede Smedes, Sebastien Jacquet
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Patent number: 6081214Abstract: An A/D conversion device includes: an amplifier AMP provided with regulating means controlled by a control signal OC or GC for adjusting the value of its output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into digital signals.The device includes means S0 or MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALOS or CALG is active, and at least a calibration arrangement DEC0 or DECM each havinga module comparing the output of the second converter ADC2 with a predetermined binary word,a module supplying the control signal OC or GC whose value depends on the result of said comparison, andmeans for storing the control signal OC or GC when the corresponding calibration signal CALOS or CALG is inactive.Type: GrantFiled: March 16, 1998Date of Patent: June 27, 2000Assignee: U.S. Philips CorporationInventors: Richard Morisson, Philippe Gandy, Frederic Darthenay
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Patent number: 6069577Abstract: An A/D conversion device includes:an amplifier AMP receiving an input voltage V1 and supplying an output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into a digital signal by comparing it with reference voltages generated by a resistance ladder R2 traversed by a bias current.The device includes a multiplexer MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALG is active, and a calibration arrangement DECM which compares the output of the second converter ADC2 with a predetermined binary word, supplies a control signal GC, which depends on the result of said comparison and determines the value of the bias current, and stores the control signal GC when the calibration signal CALG is inactive.Type: GrantFiled: March 16, 1998Date of Patent: May 30, 2000Assignee: U.S. Philips CorporationInventors: Richard Morisson, Philippe Gandy, Frederic Darthenay
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Patent number: 5923213Abstract: An amplifying device has a decibel gain that evolves quasi-linearly as a function of the digital value of a control word C(O:M-1). The device includes: an amplifying stage with K amplifiers having mutually different decibel gains, the gain in decibels of each amplifier being a multiple of the same value G0; a switching stage with K switches; a gain-controlled amplifier having a gain which varies between 0 and G0 as a function of the value of the N least significant bits (C(O:N-1)) of the control word received at its digital input; and a decoder receiving a digital word including the (M-N) most significant bits (C(N:M-1)) of the control word. The decoder has K logic outputs controlling the K switches.Type: GrantFiled: July 9, 1997Date of Patent: July 13, 1999Assignee: U.S. Philips CorporationInventors: Frederic Darthenay, Richard Morisson, Denis Raoulx
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Patent number: 5917380Abstract: The invention relates to a digitally gain-controlled amplifier including a transconductance stage provided with means for producing, at each of its N current outputs, a current (Itr) having a variable component which is representative of the analog input voltage. The amplifier also includes a switching stage comprising N switches each controlling the activation or deactivation of one of the N current outputs of the transconductance stage. Finally, the amplifier has a current/voltage conversion stage having one voltage output constituting the analog output of the amplifier and supplying a voltage which is representative of the currents received at its N current inputs.Type: GrantFiled: June 12, 1997Date of Patent: June 29, 1999Assignee: U.S. Philips CorporationInventors: Frederic Darthenay, Richard Morisson, Denis Raoulx