Abstract: Systems and methods for providing voltage regulators with sliced pole tracking are discussed. In some embodiments, a voltage regulator may include: an error amplifier, a voltage-to-current converter coupled to the error amplifier, and a current-to-current converter coupled to the voltage-to-current converter, where the current-to-current converter comprises a sliced pole tracking circuit coupled to a power device, and where the power device is configured to provide an output voltage to a load.

Abstract: A receiver path circuit includes a first stage, a down-sampler and a second stage. The first stage is configured to filter a mixer-output-signal received from a mixer and provide a first-stage-output-signal. The down-sampler is configured to down-sample the first-stage-output-signal to provide a transition-signal having a transition-frequency. The transition-frequency is lower than the frequency of the first-stage-output-signal. The second stage includes a switched-capacitor circuit that is configured to filter and reduce the frequency of the transition-signal in order to provide a second-stage-output-signal to an ADC.

Abstract: An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

Abstract: We disclose an apparatus for determining one or more calibration values of an ADC, the apparatus configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal comprising the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal comprising the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal, the apparatus configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

Abstract: RF repeater circuits may be used to regenerate an RF signal. A method and apparatus is described for regenerating a received RF signal the RF signal comprising a plurality of channels, each channel comprising a plurality of channel symbols, the method comprising producing a digitized RF signal from the received RF signal, extracting spectral information of each of the channels from the digitized RF signal, recovering one or more channel symbols from each of the plurality of channels, remodulating the channel symbols, and converting the remodulated channel symbols to an analog signal resulting in a regenerated RF signal.

Abstract: RF repeater circuits may be used to regenerate an RF signal. A method and apparatus is described for regenerating a received RF signal the RF signal comprising a plurality of channels, each channel comprising a plurality of channel symbols, the method comprising producing a digitized RF signal from the received RF signal, extracting spectral information of each of the channels from the digitized RF signal, recovering one or more channel symbols from each of the plurality of channels, remodulating the channel symbols, and converting the remodulated channel symbols to an analog signal resulting in a regenerated RF signal.

Abstract: A track and hold circuit has a main transistor for which the gate voltage is provided by a buffer circuit which is supplied with a different voltage supply than the circuit of the main transistor. This avoids the need for a bootstrap circuit.

Abstract: An electrostatic discharge protection structure (200) for an integrated circuit, the electrostatic discharge protection structure (200) comprising: a first silicon controlled rectifier structure (211) having a first triggering voltage, the first rectifier structure (211) being directly connected to an input (250) of the electrostatic discharge protection structure (200); a second silicon controlled rectifier structure (222) having a second triggering voltage lower than the first triggering voltage, the second rectifier structure (222) being connected to the input (250) via a resistor (221); and a secondary over-voltage protection unit (231) connected to the input (250) via the resistor (221).

Abstract: The present invention relates to a memory device including a capacitive element C1, a terminal of which is connected via a switch SW1 to an input intended to receive an input signal Vccd. According to the invention, the switch SW1 comprises a first and a second bipolar transistor T1 and T2 whose main current paths are arranged head to end between the input and capacitive element C1, and is also provided with control means for alternately extracting or injecting current from or into the bases of the first and second transistors T1 and T2. The invention allows memorization of the value of the input signal Vccd at a high sampling frequency and a low noise level as compared with that of known memory devices.

Abstract: The invention relates to an interface circuit FE intended to receive a pseudo-periodical input signal Vin having a reference level and a video level, and to supply a signal Vs having a level which is representative of the difference between the reference level and the video level, said interface circuit comprising: two sampling branches BR1 and BR2 simultaneously supplying the reference level and the video level, and a subtracter SUB having inputs which receive the outputs of the branches BR1 and BR2. According to the invention, the inputs of the branches BR1 and BR2 are jointly connected via a first capacitance C1 to the input of the interface circuit FE, which comprises control means CM allowing adjustment of the values of the signals at the inputs of the subtracter SUB so that they are equal when they are representative of one and the same reference level.

Abstract: An A/D conversion device includes: an amplifier AMP provided with regulating means controlled by a control signal OC or GC for adjusting the value of its output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into digital signals.The device includes means S0 or MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALOS or CALG is active, and at least a calibration arrangement DEC0 or DECM each havinga module comparing the output of the second converter ADC2 with a predetermined binary word,a module supplying the control signal OC or GC whose value depends on the result of said comparison, andmeans for storing the control signal OC or GC when the corresponding calibration signal CALOS or CALG is inactive.

Abstract: An A/D conversion device includes:an amplifier AMP receiving an input voltage V1 and supplying an output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into a digital signal by comparing it with reference voltages generated by a resistance ladder R2 traversed by a bias current.The device includes a multiplexer MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALG is active, and a calibration arrangement DECM which compares the output of the second converter ADC2 with a predetermined binary word, supplies a control signal GC, which depends on the result of said comparison and determines the value of the bias current, and stores the control signal GC when the calibration signal CALG is inactive.

Abstract: An amplifying device has a decibel gain that evolves quasi-linearly as a function of the digital value of a control word C(O:M-1). The device includes: an amplifying stage with K amplifiers having mutually different decibel gains, the gain in decibels of each amplifier being a multiple of the same value G0; a switching stage with K switches; a gain-controlled amplifier having a gain which varies between 0 and G0 as a function of the value of the N least significant bits (C(O:N-1)) of the control word received at its digital input; and a decoder receiving a digital word including the (M-N) most significant bits (C(N:M-1)) of the control word. The decoder has K logic outputs controlling the K switches.

Abstract: The invention relates to a digitally gain-controlled amplifier including a transconductance stage provided with means for producing, at each of its N current outputs, a current (Itr) having a variable component which is representative of the analog input voltage. The amplifier also includes a switching stage comprising N switches each controlling the activation or deactivation of one of the N current outputs of the transconductance stage. Finally, the amplifier has a current/voltage conversion stage having one voltage output constituting the analog output of the amplifier and supplying a voltage which is representative of the currents received at its N current inputs.