Abstract: Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.

Abstract: A multi-core audio processor includes an audio fabric block configured to organize data received from a plurality of audio interfaces into streams for processing by a plurality of digital signal processing cores. The plurality of digital signal processing cores include a single sample processing core and a frame processing core. The multi-core audio processor also includes a pool of undedicated random access memory (RAM) and a main controller configured to dynamically allocate memory resources from the pool of undedicated RAM amongst one or more of the plurality of digital signal processing cores.

Abstract: Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.

Abstract: A multi-core audio processor includes an audio fabric block configured to organize data received from a plurality of audio interfaces into streams for processing by a plurality of digital signal processing cores. The plurality of digital signal processing cores include a single sample processing core and a frame processing core. The multi-core audio processor also includes a pool of undedicated random access memory (RAM) and a main controller configured to dynamically allocate memory resources from the pool of undedicated RAM amongst one or more of the plurality of digital signal processing cores.

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive path and passivation layers disposed over the underlying dielectric layer wherein the conductive pad forms an electrically conductive path over at least a portion of the plates and diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive path and passivation layers disposed over the underlying dielectric layer wherein the conductive pad forms an electrically conductive path over at least a portion of the plates and diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive path and passivation layers disposed over the underlying dielectric layer wherein the conductive pad forms an electrically conductive path over at least a portion of the plates and diffuses electrostatic charges at the surface of the integrated circuit.