Abstract: Automatic generation of a timed delay for a timing clock signal input to an electronic device having a time critical circuit receiving address, data, and control signals at a first time interval and performing data storage and data output operations at subsequent second time intervals as determined by the timing clock signal input thereto. The time delay is generated by combination of a first control device for determining a timing condition of the time critical circuit in accordance with data output results corresponding to a first data storage operation performed by the time critical circuit; and, a second control circuit for automatically adjusting the input of the timing clock signal in time with respect to the first time interval in accordance with the data output results. Adjustment of the timing clock signal delay for subsequent data storage operations optimizes time critical circuit performance for the electronic device.