Patents by Inventor Frederic Gianesello
Frederic Gianesello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8712466Abstract: A multichannel splitter formed from 1 to 2 splitters, wherein: an input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter; the 1 to 2 splitters are electrically series-connected; and first respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.Type: GrantFiled: November 22, 2011Date of Patent: April 29, 2014Assignee: STMicroelectronics SAInventors: Baudouin Martineau, Olivier Richard, Frédéric Gianesello
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Publication number: 20140091881Abstract: A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation.Type: ApplicationFiled: September 18, 2013Publication date: April 3, 2014Applicant: STMicroelectronics SAInventors: Jean-Christophe Ricard, Cedric Durand, Frederic Gianesello
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Patent number: 8581412Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.Type: GrantFiled: October 1, 2010Date of Patent: November 12, 2013Assignee: STMicroelectronics S.A.Inventors: Romain Pilard, Daniel Gloria, Frederic Gianesello, Cedric Durand
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Patent number: 8390401Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically coupled together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.Type: GrantFiled: May 19, 2009Date of Patent: March 5, 2013Assignee: STMicroelectronics, SAInventors: Sébastien Pruvost, Frédéric Gianesello
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Publication number: 20130026846Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.Type: ApplicationFiled: July 25, 2012Publication date: January 31, 2013Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Frederic Gianesello, Romain Pilard, Cedric Durand
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Publication number: 20120190316Abstract: A multichannel splitter formed from 1 to 2 splitters, wherein: an input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter; the 1 to 2 splitters are electrically series-connected; and first respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.Type: ApplicationFiled: November 22, 2011Publication date: July 26, 2012Applicant: STMicroelectronics SAInventors: Baudouin Martineau, Olivier Richard, Frédéric Gianesello
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Publication number: 20120190317Abstract: A multichannel combiner formed from 2 to 1 combiners, wherein: a first input channel of each 2 to 1 combiner is connected to the output of a settable-gain amplifier of a signal to be combined; all 2 to 1 combiners are electrically connected in series; and an output of a first 2 to 1 combiner defines an output of the multichannel combiner.Type: ApplicationFiled: January 20, 2012Publication date: July 26, 2012Inventors: Baudouin Martineau, Olivier Richard, Frédéric Gianesello
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Patent number: 7986210Abstract: An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.Type: GrantFiled: September 8, 2009Date of Patent: July 26, 2011Assignee: STMicroelectronics, SAInventor: Frederic Gianesello
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Patent number: 7982571Abstract: An inductance formed in a stack of insulating layers, the inductance comprising first and second access terminals and first and second half-loops distributed in the stack of insulating layers on a number of distinct levels greater than or equal to four. For each level, each first half-loop is at least partly symmetrical to one of the second half-loops. All the first half-loops are series-connected according to a first succession of first half-loops to form first loops between the first access terminal and a midpoint and all the second half-loops are series-connected according to a second succession of second half-loops to form second loops between the second output terminal and the midpoint.Type: GrantFiled: July 25, 2008Date of Patent: July 19, 2011Assignee: STMicroelectronics S.A.Inventor: Frédéric Gianesello
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Publication number: 20110109521Abstract: An electronic device includes a semiconductor component having a support substrate in the form of a wafer. On one side of this substrate integrated circuits including an RF circuit and an antenna connected to this RF circuit are formed. A metal layer is situated on the other side of the substrate, facing the antenna. At least on metal via is provided in a through-hole in the substrate, this via being connected at one end to the metal layer and at the other end to the RF circuit, at the same reference potential node as the antenna.Type: ApplicationFiled: November 8, 2010Publication date: May 12, 2011Applicant: STMicroelectronics S.A.Inventors: Romain Pilard, Daniel Gloria, Frederic Gianesello, Cedric Durand
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Publication number: 20110084398Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.Type: ApplicationFiled: October 1, 2010Publication date: April 14, 2011Applicant: STMICROELECTRONICS S.A.Inventors: Romain Pilard, Daniel Gloria, Frederic Gianesello, Cedric Durand
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Publication number: 20110057759Abstract: Integrated inductive device comprising a central loop arranged between two outer loops mutually coupled to the central loop so as to form two patterns roughly in the form of an eight having a common portion corresponding to said central loop.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Applicant: STMicroelectronics SAInventor: Frederic Gianesello
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Patent number: 7768372Abstract: An inductance formed in a stacking of insulating layers, the inductance comprising first and second half-turns, each first half-turn being at least partly symmetrical to one of the second half-turns, the first half-turns being distributed in first groups of first half-turns at least partly aligned along the insulating layer stacking direction and the second half-turns being distributed in second groups of second half-turns at least partly aligned along the insulating layer stacking direction. For any pair of first adjacent half-turns of a same group, one of the first half-turns in the pair is electrically series-connected to the other one of the first half-turns in the pair by a single second half turn and for each pair of second adjacent half-turns of a same group, one of the second half-turns in the pair is electrically series-connected to the other one of the second half-turns in the pair by a single first half-turn.Type: GrantFiled: July 17, 2008Date of Patent: August 3, 2010Assignee: STMicroelectronics, SAInventor: Frederic Gianesello
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Publication number: 20100073118Abstract: An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.Type: ApplicationFiled: September 8, 2009Publication date: March 25, 2010Inventor: Frederic Gianesello
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Publication number: 20090284331Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.Type: ApplicationFiled: May 19, 2009Publication date: November 19, 2009Applicant: STMICROELECTRONICS SAInventors: Sebastien Pruvost, Frederic Gianesello
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Patent number: 7586195Abstract: An electronic component for microwave transmission includes a high resistivity substrate on which is at least located several metallization layers divided into portions. A first set of piled up portions defines a ground ribbon and a second set of piled up portions defines a power ribbon. At least a first active portion of said ground ribbon and a first active portion of said power ribbon are respectively located between the substrate and an uppermost one of the several metallization layers. The electronic component in one implementation is a coplanar waveguide.Type: GrantFiled: October 2, 2006Date of Patent: September 8, 2009Assignee: STMicroelectronics S.A.Inventors: Sébastien Pruvost, Frédéric Gianesello
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Publication number: 20090027152Abstract: An inductance formed in a stacking of insulating layers, the inductance comprising first and second half-turns, each first half-turn being at least partly symmetrical to one of the second half-turns, the first half-turns being distributed in first groups of first half-turns at least partly aligned along the insulating layer stacking direction and the second half-turns being distributed in second groups of second half-turns at least partly aligned along the insulating layer stacking direction. For any pair of first adjacent half-turns of a same group, one of the first half-turns in the pair is electrically series-connected to the other one of the first half-turns in the pair by a single second half turn and for each pair of second adjacent half-turns of a same group, one of the second half-turns in the pair is electrically series-connected to the other one of the second half-turns in the pair by a single first half-turn.Type: ApplicationFiled: July 17, 2008Publication date: January 29, 2009Inventor: Frederic Gianesello
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Publication number: 20090027150Abstract: An inductance formed in a stack of insulating layers, the inductance comprising first and second access terminals and first and second half-loops distributed in the stack of insulating layers on a number of distinct levels greater than or equal to four. For each level, each first half-loop is at least partly symmetrical to one of the second half-loops. All the first half-loops are series-connected according to a first succession of first half-loops to form first loops between the first access terminal and a midpoint and all the second half-loops are series-connected according to a second succession of second half-loops to form second loops between the second output terminal and the midpoint.Type: ApplicationFiled: July 25, 2008Publication date: January 29, 2009Applicant: STMicroelectronics S.A.Inventor: Frederic Gianesello
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Publication number: 20080079170Abstract: An electronic component for microwave transmission includes a high resistivity substrate on which is at least located several metallization layers divided into portions. A first set of piled up portions defines a ground ribbon and a second set of piled up portions defines a power ribbon. At least a first active portion of said ground ribbon and a first active portion of said power ribbon are respectively located between the substrate and an uppermost one of the several metallization layers. The electronic component in one implementation is a coplanar waveguide.Type: ApplicationFiled: October 2, 2006Publication date: April 3, 2008Applicant: STMicroelectronics S.A.Inventors: Sebastien Pruvost, Frederic Gianesello