Patents by Inventor Frederic Greus
Frederic Greus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20260277758Abstract: An electronic system includes a network-on-chip (NoC) and a fault aggregation circuit. The NoC includes a plurality of NoC components that generate faults. The fault aggregation circuit is configured to receive the faults from the NoC components and aggregate and remap the faults into a few alarm levels.Type: ApplicationFiled: March 14, 2025Publication date: September 17, 2026Applicant: ARTERIS, INC.Inventors: Xavier VAN RUYMBEKE, Michael MORIAUD, Jean-Christophe PELLION, Frederic GREUS, Christopher PEZLEY
-
Patent number: 12724708Abstract: In an electronic system, data is written to a write address in register memory. Chunks of the data are decomposed into a plurality of data sub-granules. Bits of the write address are distributed to the data sub-granules. An address sub-granule is created for any bits of the write address that were not distributed to the data sub-granules. A resilience algorithm is used to compute resilience bits for each of the sub-granules. The chunks and the resilience bits are written to the register memory.Type: GrantFiled: March 30, 2025Date of Patent: September 1, 2026Assignee: ARTERIS, INC.Inventors: Xavier Van Ruymbeke, Michael Moriaud, Frederic Greus, Sylvain Meliciani
-
Publication number: 20250315584Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: ApplicationFiled: June 23, 2025Publication date: October 9, 2025Applicant: ARTERIS, INC.Inventors: John Coddington, Sylvain MELICIANI, Frederic GREUS, Xavier Van RUYMBEKE
-
Patent number: 12340156Abstract: A system and method for generation of a hardware description for adding interface protection scheme to an electronic design. The electronic design and interface protection scheme are defined as parameters. An interface protection model includes interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description module uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding.Type: GrantFiled: December 13, 2023Date of Patent: June 24, 2025Assignee: ARTERIS, INC.Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
-
Publication number: 20240160822Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: ApplicationFiled: December 13, 2023Publication date: May 16, 2024Applicant: ARTERIS, INC.Inventors: John Coddington, Sylvain MELICIANI, Frederic GREUS, Xavier Van RUYMBEKE
-
Patent number: 11847394Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: GrantFiled: December 2, 2021Date of Patent: December 19, 2023Assignee: Arteris, Inc.Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
-
Publication number: 20220180034Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: ApplicationFiled: December 2, 2021Publication date: June 9, 2022Applicant: Arteris, Inc.Inventors: John CODDINGTON, Sylvain MELICIANI, Frederic GREUS, Xavier Van RUYMBEKE
-
Patent number: 11210445Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: GrantFiled: December 9, 2020Date of Patent: December 28, 2021Assignee: ARTERIS, INC.Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke