Patents by Inventor Frederic Hasbani
Frederic Hasbani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10181855Abstract: An integrated circuit includes a first logic circuit region comprising a first regional clock network for supplying a first regional clock signal to digital logic circuit(s); and a clock gating circuit to derive the first regional clock signal from a clock signal and selectively apply and interrupt the first regional clock signal in accordance with a state select signal. The first logic circuit region comprises a first back bias voltage grid connected to respective bodies of PMOS transistors of the digital logic circuit(s) and a second back bias voltage grid connected to respective bodies of NMOS transistors of the digital logic circuit(s). The integrated circuit further comprises a controllable back bias voltage generator configured to adjust a first back bias voltage of the first back bias voltage grid, and to adjust a back bias voltage of the second back bias voltage grid, in accordance with the state select signal.Type: GrantFiled: August 14, 2017Date of Patent: January 15, 2019Assignee: GN Hearing A/SInventors: Dan Raun Jensen, Per Asbeck, Frederic Hasbani
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Publication number: 20180183440Abstract: An integrated circuit includes a first logic circuit region comprising a first regional clock network for supplying a first regional clock signal to digital logic circuit(s); and a clock gating circuit to derive the first regional clock signal from a clock signal and selectively apply and interrupt the first regional clock signal in accordance with a state select signal. The first logic circuit region comprises a first back bias voltage grid connected to respective bodies of PMOS transistors of the digital logic circuit(s) and a second back bias voltage grid connected to respective bodies of NMOS transistors of the digital logic circuit(s). The integrated circuit further comprises a controllable back bias voltage generator configured to adjust a first back bias voltage of the first back bias voltage grid, and to adjust a back bias voltage of the second back bias voltage grid, in accordance with the state select signal.Type: ApplicationFiled: August 14, 2017Publication date: June 28, 2018Applicant: GN Hearing A/SInventors: Dan Raun JENSEN, Per ASBECK, Frederic HASBANI
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Patent number: 9461641Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.Type: GrantFiled: October 24, 2013Date of Patent: October 4, 2016Assignee: STMicroelectronics SAInventors: Severin Trochut, Emilie Rigal, Fabrice Blisson, Frederic Hasbani, Nicolas Seller
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Patent number: 9147695Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.Type: GrantFiled: December 4, 2013Date of Patent: September 29, 2015Assignee: STMICROELECTRONICS SAInventors: Frédéric Hasbani, Eric Remond
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Patent number: 9013228Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.Type: GrantFiled: January 21, 2014Date of Patent: April 21, 2015Assignee: STMicroelectronics SAInventor: Frédéric Hasbani
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Publication number: 20140167527Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.Type: ApplicationFiled: October 24, 2013Publication date: June 19, 2014Applicant: STMicroelectronics SAInventors: Severin Trochut, Emilie Rigal, Fabrice Blisson, Frederic Hasbani, Nicolas Seller
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Publication number: 20140167167Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.Type: ApplicationFiled: December 4, 2013Publication date: June 19, 2014Applicant: STMICROELECTRONICS SAInventors: Frederic HASBANI, Eric Remond
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Publication number: 20140132338Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: STMicroelectronics SAInventor: Frédéric Hasbani
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Publication number: 20120049812Abstract: A switched-mode converter includes first and second chopper transistors, and control means for maintaining the first and second chopper transistors respectively on and off during first operating phases. The first and second chopper transistors are maintained respectively off and on during second operating phases. An intermediary voltage is applied to the gate of the second transistor during intermediary phases taking place between the first and second phases. This intermediary voltage is close to the threshold voltage of the second transistor.Type: ApplicationFiled: August 24, 2011Publication date: March 1, 2012Applicant: STMicroelectronics SAInventors: Vincent Pinon, Frédéric Hasbani
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Publication number: 20080049872Abstract: A device for matching an output impedance of a transmitter includes at least a first output terminal connected to a first static impedance external to said transmitter and forming a component of an equivalent static load, and a first programmable resistive component in series with the first impedance. The device further includes a reference voltage generator internal to said transmitter, a comparator receiving the reference voltage and a measurement voltage representative of the voltage on the terminals of the load as seen by the transmitter and generating a comparison signal representative of the comparison result, and a control unit generating a control signal depending on the comparison signal, in order to control at least the programmable resistive component.Type: ApplicationFiled: August 17, 2007Publication date: February 28, 2008Applicant: STMicroelectronics S.A.Inventors: Christophe Fourtou, Frederic Hasbani
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Patent number: 6791340Abstract: A device for the comparison of two resistors is based upon analog information carried by currents. The device includes a measurement circuit for extracting the currents from the two resistors to be compared, and copies the currents to a parallel analog-digital converter that carries out the division of the extracted currents. The device converts the ratio of the extracted currents into a digital code that is the image of the ratio of the two resistors. The ratio is constantly re-updated as a function of environmental parameters of the circuit, such as the operating temperature. Also disclosed is a system for correcting the value of integrated compensated resistors. The system implements a device of this kind that does not use a reference voltage generator.Type: GrantFiled: June 12, 2002Date of Patent: September 14, 2004Assignee: STMicroelectronics SAInventor: Frédéric Hasbani
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Publication number: 20030001594Abstract: A device for the comparison of two resistors is based upon analog information carried by currents. The device includes a measurement circuit for extracting the currents from the two resistors to be compared, and copies the currents to a parallel analog-digital converter that carries out the division of the extracted currents. The device converts the ratio of the extracted currents into a digital code that is the image of the ratio of the two resistors. The ratio is constantly re-updated as a function of environmental parameters of the circuit, such as the operating temperature. Also disclosed is a system for correcting the value of integrated compensated resistors. The system implements a device of this kind that does not use a reference voltage generator.Type: ApplicationFiled: June 12, 2002Publication date: January 2, 2003Applicant: STMicroelectronics S.A.Inventor: Frederic Hasbani