Patents by Inventor Frederic Hayem
Frederic Hayem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160226530Abstract: A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.Type: ApplicationFiled: February 5, 2016Publication date: August 4, 2016Applicant: Broadcom CorporationInventors: Frederic HAYEM, Leo Borromeo, Michiel Lotter
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Patent number: 9282589Abstract: A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.Type: GrantFiled: March 18, 2013Date of Patent: March 8, 2016Assignee: Broadcom CorporationInventors: Frederic Hayem, Leo Borromeo, Michiel Lotter
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Patent number: 8532701Abstract: A multi-mode communication device is disclosed and includes a host baseband processor configured to operate in a first communications system of a plurality of communications systems, and a baseband co-processor configured to operate in a second communications system of the plurality of communications systems. The second communications system is different from the first communications system. The host baseband processor is operable to time synchronize the second communications system to the first communications system based on timing information generated by the baseband co-processor. The host baseband processor may include circuitry for issuing, from the host baseband processor, a timer capture interrupt to the baseband co-processor during a predetermined timer phase of the first communications system.Type: GrantFiled: August 23, 2011Date of Patent: September 10, 2013Assignee: Broadcom CorporationInventors: Frederic Hayem, Leo Borromeo, Michiel Lotter
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Patent number: 8423077Abstract: A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.Type: GrantFiled: December 11, 2003Date of Patent: April 16, 2013Assignee: Broadcom CorporationInventors: Frederic Hayem, Leo Borromeo, Michiel Lötter
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Patent number: 8161217Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: GrantFiled: July 19, 2011Date of Patent: April 17, 2012Assignee: Broadcom CorporationInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Publication number: 20120052906Abstract: A multi-mode communication device is disclosed and includes a host baseband processor configured to operate in a first communications system of a plurality of communications systems, and a baseband co-processor configured to operate in a second communications system of the plurality of communications systems. The second communications system is different from the first communications system. The host baseband processor is operable to time synchronize the second communications system to the first communications system based on timing information generated by the baseband co-processor. The host baseband processor may include circuitry for issuing, from the host baseband processor, a timer capture interrupt to the baseband co-processor during a predetermined timer phase of the first communications system.Type: ApplicationFiled: August 23, 2011Publication date: March 1, 2012Inventors: Frederic Hayem, Leo Borromeo, Michiel Lötter
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Publication number: 20110276736Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: BROADCOM CORPORATIONInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Patent number: 8005503Abstract: A method for effecting timing synchronization within a multi-mode communication device is disclosed herein. The method includes configuring a host baseband processor of the multi-mode device to operate in accordance with a first wireless communications protocol of a first wireless communications system. A baseband co-processor of the device is also configured to operate in accordance with a second wireless communications protocol of a second wireless communications system. The method includes establishing, within the device, timing synchronization between the first and second communication systems on the basis of timing information transferred to the host baseband processor from the baseband co-processor.Type: GrantFiled: December 11, 2003Date of Patent: August 23, 2011Inventors: Frederic Hayem, Leo Borromeo, Michiel Lötter
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Patent number: 7984216Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: GrantFiled: August 18, 2009Date of Patent: July 19, 2011Assignee: Broadcom CorporationInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Patent number: 7716528Abstract: Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.Type: GrantFiled: November 30, 2004Date of Patent: May 11, 2010Assignee: Broadcom CorporationInventor: Frederic Hayem
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Publication number: 20090307402Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Applicant: BROADCOM CORPORATIONInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Patent number: 7577779Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: GrantFiled: February 14, 2006Date of Patent: August 18, 2009Assignee: Broadcom CorporationInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Publication number: 20070242651Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: ApplicationFiled: February 14, 2006Publication date: October 18, 2007Inventors: Frederic Hayem, Andrew Preez, Louis Botha, Johan Conroy
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Publication number: 20070191007Abstract: Certain aspects of a method and system for handling signals in a communication system are disclosed. Aspects of one method may include processing, within a single chip, any one of a plurality of wireless access communication protocols by any one of a plurality of on-chip baseband processors. None of the on-chip baseband processors is a dedicated processor that is configured to handle only a single wireless access communication protocol. The plurality of wireless access communication protocols may comprise WCDMA, HSDPA, GSM, GPRS, and EDGE. Any one of the plurality of on-chip baseband processors may be configured to process any one of the plurality of wireless access communication protocols.Type: ApplicationFiled: February 14, 2006Publication date: August 16, 2007Inventors: Claude Hayek, Lawrence Madar, Nelson Sollenberger, Frederic Hayem, Vafa Rakshani
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Publication number: 20060053343Abstract: Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.Type: ApplicationFiled: November 30, 2004Publication date: March 9, 2006Inventor: Frederic Hayem
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Publication number: 20040185899Abstract: A method for effecting timing synchronization within a multi-mode communication device is disclosed herein. The method includes configuring a host baseband processor of the multi-mode device to operate in accordance with a first wireless communications protocol of a first wireless communications system. A baseband co-processor of the device is also configured to operate in accordance with a second wireless communications protocol of a second wireless communications system. The method includes establishing, within the device, timing synchronization between the first and second communication systems on the basis of timing information transferred to the host baseband processor from the baseband co-processor.Type: ApplicationFiled: December 11, 2003Publication date: September 23, 2004Inventors: Frederic Hayem, Leo Borromeo, Michiel Lotter
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Publication number: 20040176059Abstract: A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.Type: ApplicationFiled: December 11, 2003Publication date: September 9, 2004Inventors: Frederic Hayem, Leo Borromeo, Michiel Lotter
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Patent number: 6546514Abstract: A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion. The method includes identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals representing an unknown state in response to conditions under which the first defective portion is likely to malfunction.Type: GrantFiled: December 13, 1999Date of Patent: April 8, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Frederic Hayem, Patrick Arnould
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Patent number: 6118314Abstract: The present invention includes a circuit assembly and method of synchronizing plural circuits. According to one aspect of the present invention, a circuit includes: an oscillator configured to generate a reference clock signal; a first circuit including: a first divider configured to generate a first internal clock signal responsive to the reference clock signal; and reset generation circuitry configured to receive an external reset signal and generate a reset second circuit signal synchronized with a predefined position of the first divider, with the reference clock signal and with the external reset signal; and a second circuit including: reset detection circuitry configured to generate a reset detection signal synchronized with the reset second circuit signal and the reference clock signal; and a second divider configured to set to a predefined position responsive to the reception of the reset detection signal and generate a second internal clock signal synchronized with the first internal clock signal.Type: GrantFiled: October 14, 1998Date of Patent: September 12, 2000Assignee: VLSI Technology, Inc.Inventors: Patrick Arnould, Frederic Hayem