Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided.

Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided.

Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry.

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction.

Abstract: An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry.

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction.

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialization instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialization instruction SSI added to a second issue queue 10. The master serialization instruction MSI manages serialization relative to the instructions within the first issue queue 8. The slave serialization instruction SSI manages serialization relative to the instructions within the second issue queue 10. The master serialization instruction MSI and the slave serialization instruction SSI are removed when both have met their serialization conditions and are respectively the oldest instructions within their issue queues.

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.