Abstract: A method for controlling a pixel may include first and second photosites, each having a photodiode and a charge-transfer transistor, a read node, and an electronic read element, all of which are common to all the photosites. The method may include an accumulation of photogenerated charges in the photodiode of the first photosite during a first period, an accumulation of photogenerated charges in the photodiode of the second photosite during a second period shorter than the first period, a selection of the signal corresponding to the quantity of charges accumulated in the photodiode of a photosite having the highest unsaturated intensity or else a saturation signal, and a digitization of the selected signal.

Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.