Abstract: A Schottky diode includes a substrate with an active region. Sidewall and bottom surfaces of trench extending into an epitaxial layer of the substrate are lined with an insulating layer, and the remainder of each trench is filled with a polycrystalline silicon (polysilicon) fill. A doped region having the same conductivity type dopant as the semiconductor substrate is implanted in the epitaxial layer at locations between adjacent trenches. A silicide is provided at each polysilicon fill and a Schottky barrier is provided at each doped region. An anode contact for the diode contacts the silicide and Schottky barrier, and a cathode contact for the diode contacts a lower surface of the substrate. The selection of a dopant concentration level for the doped region controls setting of a forward voltage VF level for the Schottky diode.

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

Abstract: The present description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type and coated, on the upper side thereof, with a semiconductor layer doped with the first conductivity type. The component includes: an active region (100A); and first and second groups of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending vertically into the thickness of the semiconductor layer from the upper side thereof; and a second field limiting ring laterally interposed between the first and second groups of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically into the thickness of the semiconductor layer from the upper face thereof.

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

Abstract: A circuit includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor includes a first diode with drain, source, gate and first additional electrodes. The second field-effect transistor includes a second diode with drain, source, gate and second additional electrodes. A first switch selectively connects the gate and drain electrodes of the first field-effect transistor. A second switch selectively connects the gate and drain electrodes of the second field-effect transistor. A control circuit controls the first and second switches. The first additional electrode is coupled to the gate electrode of the second field-effect transistor, and the second additional electrode is coupled to the gate electrode of the first field-effect transistor.

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

Abstract: A circuit includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor includes a first diode with drain, source, gate and first additional electrodes. The second field-effect transistor includes a second diode with drain, source, gate and second additional electrodes. A first switch selectively connects the gate and drain electrodes of the first field-effect transistor. A second switch selectively connects the gate and drain electrodes of the second field-effect transistor. A control circuit controls the first and second switches. The first additional electrode is coupled to the gate electrode of the second field-effect transistor, and the second additional electrode is coupled to the gate electrode of the first field-effect transistor.

Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.

Abstract: A TMBS-type Schottky diode including main electrodes on active areas on the upper surface side and a main electrode on the lower surface side, including on the upper surface side conductive fingers penetrating between the active areas and biased, directly or indirectly, like the active areas. The fingers includes closer portions on their upper portion side than on their bottom side. The fingers preferably are polysilicon fingers insulated by an insulating layer such as silicon oxide.

Abstract: A Schottky diode with a vertical barrier extending perpendicularly to the surface of a semiconductor chip having a vertical central metal conductor in contact on the one hand with the substrate of the semiconductor chip with an interposed interface forming a Schottky barrier, and on the other hand with radially-extending conductive fingers.

Abstract: A vertical unipolar component formed in a semiconductor substrate, comprising vertical fingers made of a conductive material surrounded with silicon oxide, portions of the substrate being present between the fingers and the assembly being coated with a conductive layer. The component periphery includes a succession of fingers arranged in concentric trenches, separated from one another by silicon oxide only, the upper surface of the fingers of at least the innermost rank being in contact with said conductive layer.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other.

Abstract: A MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. A MOS power transistor according to the present invention alternately includes a source region of a first conductivity type, an intermediary region, and a drain region of the first conductivity type, each of these regions extending across the entire thickness of the substrate, the source and drain regions being contacted by conductive fingers or plates substantially crossing the substrate, insulated and spaced apart conductive fingers crossing from top to bottom the intermediary region, the horizontal distance between the insulated fingers being such that the intermediary region can be inverted when an appropriate voltage is applied to these insulated fingers.

Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.

Abstract: A method for manufacturing a vertical Schottky diode with a guard ring on a lightly-doped N-type silicon carbide layer, comprising the steps of forming a P-type epitaxial layer on the N-type layer; implanting N-type dopants in areas of the P-type epitaxial layer to neutralize in these areas, across the entire thickness of the epitaxial layer, the P-type dopants to form N-type regions, of dopant concentration lower than that of the epitaxial layer, and delimiting a P-type guard ring; forming on the external periphery of the component an insulating layer partially covering the guard ring; and forming a Schottky contact with the N-type region internal to the guard ring.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions (34) with a first type of conductivity (P) which are embedded in a thick layer (32) with a second type of conductivity (N). Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material.