Abstract: Heterojunction structure, also referred to as a heterostructure, of semiconductor material, in particular for a high electron mobility transistor (HEMT), includes a substrate, a stack of at least three buffer layers of a same semiconductor material with a wide bandgap EG1 based on a column-III nitride, namely an unintentionally doped first buffer layer, a second buffer layer, an unintentionally doped third buffer layer, an unintentionally doped intermediate layer, and a barrier layer arranged on the intermediate layer, said barrier layer being of a semiconductor material with a wide bandgap EG2 based on a column-III nitride; the second buffer layer has constant P+ doping throughout some or all of its thickness; and the third buffer layer includes a first region which is unintentionally doped throughout its entire thickness and at least one second region adjacent to said first region with N+ doping surrounding the first region.

Abstract: Heterojunction structure, also referred to as a heterostructure, of semiconductor material, in particular for a high electron mobility transistor (HEMT), includes a substrate, a stack of at least three buffer layers of a same semiconductor material with a wide bandgap EG1 based on a column-III nitride, namely an unintentionally doped first buffer layer, a second buffer layer, an unintentionally doped third buffer layer, an unintentionally doped intermediate layer, and a barrier layer arranged on the intermediate layer, said barrier layer being of a semiconductor material with a wide bandgap EG2 based on a column-III nitride; the second buffer layer has constant P+ doping throughout some or all of its thickness; and the third buffer layer includes a first region which is unintentionally doped throughout its entire thickness and at least one second region adjacent to said first region with N+ doping surrounding the first region.

Abstract: A heterojunction structure of semiconductor material, for a high electron mobility transistor includes a substrate, a buffer layer, arranged on the substrate, of a large bandgap semiconductor material, based on a nitride from column III, where the buffer layer is not intentionally doped with n-type carriers, a barrier layer arranged above the buffer layer, of a large bandgap semiconductor material based on a nitride from column III, where the width of the bandgap of the barrier layer is less than the width of the bandgap of the buffer layer. The heterojunction structure additionally comprises an intentionally doped area, of a material based on a nitride from column III identical to the material of the buffer layer, in a plane parallel to the plane of the substrate and a predefined thickness along a direction orthogonal to the plane of the substrate, where the area is comprised in the buffer layer.

Abstract: A heterojunction structure of semiconductor material, for a high electron mobility transistor includes a substrate, a buffer layer, arranged on the substrate, of a large bandgap semiconductor material, based on a nitride from column III, where the buffer layer is not intentionally doped with n-type carriers, a barrier layer arranged above the buffer layer, of a large bandgap semiconductor material based on a nitride from column III, where the width of the bandgap of the barrier layer is less than the width of the bandgap of the buffer layer. The heterojunction structure additionally comprises an intentionally doped area, of a material based on a nitride from column III identical to the material of the buffer layer, in a plane parallel to the plane of the substrate and a predefined thickness along a direction orthogonal to the plane of the substrate, where the area is comprised in the buffer layer.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: A power semiconductor device comprising an array of cells distributed over a surface of a substrate, the source regions of the individual cells of the array comprising a plurality of source region branches each extending laterally outwards towards at least one source region branch of an adjacent cell and presenting juxtaposed ends, the base regions of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches to form a single base region surrounding the source regions of the individual cells of the array in the substrate. The junctions between the merged base region and the drain region are solely concave laterally and define rounded current conduction path areas for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions to the drain electrode.

Abstract: A lateral semiconductor device (20) such as LDMOS, a LIGBT, a lateral diode, a lateral GTO, a lateral JFET or a lateral BJT, comprising a drift region (12) having a first surface (22) and a first conductivity type, first and second conductive (4, 8) extending into the drift region from the first surface. The lateral semiconductor device further comprises an additional region (24) or several additional regions, having a second conductivity type, between the first and second semiconductor regions (4, 8), the additional region extending into the drift region from the first surface (22), wherein the additional region forms a junction dividing the electric field between the first and second semiconductor regions when a current path is established between the first and second semiconductor regions. This allows the doping concentration of the drift region to be increased, thereby lowering the on-resistance of the device.

Abstract: A lateral semiconductor device (20) such as LDMOS, a UIGBT, a lateral diode, a lateral GTO, a lateral JFRT or a lateral BJT, comprising a drift region (12) having a first surface (22) and a first conductivity type, first and second conductive regions (4, 8) extending into the drift region from the first surface. The lateral semiconductor device further comprises an additional region (24) or several additional regions, having a second conductivity type, between the first and second semiconductor regions (4, 8), the additional region extending into the drift region from the first surface (22), wherein the additional region forms a junction dividing the electric field between the first and second semiconductor regions when a current path is established between the first and second semiconductor regions. This allows the doping concentration of the drift region to be increased, thereby lowering the on-resistance of the device.

Abstract: The invention concerns a Schottky-diode semiconductor device, comprising a substrate consisting of first (2) and second (3) semiconductor layers having the same type of conduction tiered up in said substrate, the second layer (3) being more highly doped than the first (2), said substrate having first (4) and second (5) main surfaces in contact with first (8) and second (6) electrodes, a Schottky barrier being formed between the first electrode (8) and said first layer. The invention is characterised in that the plurality of islands (9) having a type of conduction opposite to that of the first layer (2) are arranged in beds spaced apart in the thickness of said layer (2).