Abstract: The invention relates to a &Dgr;&Sgr; modulator including means (60, 61, 62) for measuring an error due to differences in the operating parameters of individual components of its internal D/A converter (50), and means (60, 61, 62) for applying a correction of the error measured in this way to a digital signal, the modulator being characterized in that the internal converter (50) comprises a number of individual components greater than the number necessary for internal conversion, and in that the measurement means (60, 61, 62) are suitable for extracting in alternation from the internal conversion process, on each occasion a different component from the various individual components in order to measure the operating parameter error of the extracted component, while leaving a number of components in action that is sufficient for internal conversion.

Abstract: With a switch including at least one insulated-gate field-effect transistor, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal to successively turn it on and off. On the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period and for a predetermined precharge duration, with a predetermined precharge voltage. Then, for the remaining duration of the half-period, the precharged capacitor is connected between the source and the gate of the transistor to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. At the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.

Abstract: A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.

Abstract: A digital sample filtering device comprising storage device including ROM and RAM memory for storing in an interlaced manner, coefficients of at least two filters along with for each coefficient, data indicating to which of the filters the each coefficient belongs; a multiplier for multiplying at least one of the coefficients by a sample and an accumulator for adding the partial sums of the multiplication results for each of the filters.

Abstract: A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.

Abstract: A digital-to-analog converter that includes pairs of positive and negative current sources that are connected through switches to two differential output lines. The switches are controlled as a function of a digital data. Each pair of current sources includes a pair of transistors of an output stage of a transconductance amplifier. The transconductance amplifier receives a reference voltage at a non-inverting input, and receives at an inverting input, the voltage at the middle node of a bridge of resistors that is connected between the two differential out-put lines. The output of the converter is the voltage between the two differential output lines.

Abstract: The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.

Abstract: The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.