Patents by Inventor Frederic Parain
Frederic Parain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11645129Abstract: A data structure (e.g., field, method parameter, or method return value) is defined by a descriptor to be of a particular type, which imposes a first set of restrictions on values assumable by the data structure. Separately, the data structure is associated with a type restriction that defines a second set of restrictions that further restricts the values assumable by the data structure. The descriptor and type restriction are encoded separately in a program binary. Responsive to identifying a value for the data structure that (a) is not forbidden by the first set of restrictions defined the descriptor and (b) is forbidden by the second set of restrictions defined by the type restriction, a runtime environment may perform a restrictive operation, such as: blocking storage of the value to a field; blocking passing of the value to a method parameter; or blocking return of the value from a method.Type: GrantFiled: January 7, 2022Date of Patent: May 9, 2023Assignee: Oracle International CorporationInventors: Daniel Lee Smith, John Robert Rose, Brian Goetz, Frederic Parain
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Publication number: 20220300263Abstract: A data structure (e.g., field, method parameter, or method return value) is defined by a descriptor to be of a particular type, which imposes a first set of restrictions on values assumable by the data structure. Separately, the data structure is associated with a type restriction that defines a second set of restrictions that further restricts the values assumable by the data structure. The descriptor and type restriction are encoded separately in a program binary. Responsive to identifying a value for the data structure that (a) is not forbidden by the first set of restrictions defined the descriptor and (b) is forbidden by the second set of restrictions defined by the type restriction, a runtime environment may perform a restrictive operation, such as: blocking storage of the value to a field; blocking passing of the value to a method parameter; or blocking return of the value from a method.Type: ApplicationFiled: January 7, 2022Publication date: September 22, 2022Applicant: Oracle International CorporationInventors: Daniel Lee Smith, John Robert Rose, Brian Goetz, Frederic Parain
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Patent number: 8032891Abstract: A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.Type: GrantFiled: May 20, 2002Date of Patent: October 4, 2011Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Dominique D'Inverno, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Frédéric Parain, Jean-Paul Routeau, Salam Majoul
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Patent number: 7941790Abstract: A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code modules from a plurality of available program code modules in accordance with said desired program code characteristic, and generating program code for translating high level code into instructions for said target processor from said selected one or more predefined program code modules. Preferably, the method comprises forming agglomerated program code from a plurality of program code modules in accordance with said desired program code characteristic.Type: GrantFiled: October 24, 2001Date of Patent: May 10, 2011Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Gerard Chauvel, Dominique D'Inverno, Teresa Higuera, Valerie Issarny, Serge Lasserre, Frederic Parain, Jean-Paul Routeau
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Patent number: 7565385Abstract: An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded garbage collection object preferably uses control data to cause objects to be removed from said memory, the removed objects comprise those objects that were created while an embedded garbage collection object was active and that do not have references from root objects.Type: GrantFiled: April 22, 2004Date of Patent: July 21, 2009Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Jean-Paul Routeau, Salam Majoul, Frédéric Parain
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Patent number: 7496930Abstract: In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.Type: GrantFiled: April 22, 2004Date of Patent: February 24, 2009Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Jean-Paul Routeau, Salam Majoul, Frédéric Parain
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Patent number: 7434021Abstract: A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.Type: GrantFiled: April 22, 2004Date of Patent: October 7, 2008Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Jean-Paul Routeau, Salam Majoul, Frédéric Parain
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Patent number: 7330937Abstract: A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scratchpad memory depending on the determination. Other embodiments are disclosed herein as well.Type: GrantFiled: April 5, 2004Date of Patent: February 12, 2008Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Jean-Paul Routeau, Salam Majoul, Frédéric Parain
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Publication number: 20050033945Abstract: A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).Type: ApplicationFiled: April 22, 2004Publication date: February 10, 2005Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Jean-Paul Routeau, Salam Majoul, Frederic Parain
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Publication number: 20040268076Abstract: A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.Type: ApplicationFiled: April 22, 2004Publication date: December 30, 2004Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Jean-Paul Routeau, Salam Majoul, Frederic Parain
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Publication number: 20040260904Abstract: A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scratchpad memory depending on the determination. Other embodiments are disclosed herein as well.Type: ApplicationFiled: April 5, 2004Publication date: December 23, 2004Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'lnverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Jean-Paul Routeau, Salam Majoul, Frederic Parain
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Publication number: 20040260732Abstract: An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded garbage collection object preferably uses control data to cause objects to be removed from said memory, the removed objects comprise those objects that were created while an embedded garbage collection object was active and that do not have references from root objects.Type: ApplicationFiled: April 22, 2004Publication date: December 23, 2004Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Jean-Paul Routeau, Salam Majoul, Frederic Parain
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Publication number: 20040260911Abstract: A preparation method comprises determining whether an instruction contains an unresolved reference and replacing an unresolved instruction with a predetermined instruction containing an operand associated with reference resolution code. A resolution execution method comprises receiving a plurality of instructions, at least one instruction of which comprises a replacement instruction that replaced a previous instruction, determining whether any of the received instructions comprise the replacement instruction, and executing resolution code to resolve a reference upon determining that a received instruction comprises the replacement instruction. The replacement instruction includes an operand that identifies the resolution code. A processor associated with these methods is also disclosed.Type: ApplicationFiled: April 23, 2004Publication date: December 23, 2004Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Jean-Paul Routeau, Salam Majoul, Frederic Parain
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Publication number: 20040261085Abstract: In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.Type: ApplicationFiled: April 22, 2004Publication date: December 23, 2004Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Jean-Paul Routeau, Salam Majoul, Frederic Parain
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Publication number: 20040010785Abstract: A profiling system independently creates application profiles (10) that indicate the number of executions of each operation in the application and virtual machine profiles (14) which indicate the time/energy consumed by each operation on a particular hardware platform. An application profile (10) in conjunction with the virtual machine profile (14) can be used to generate time and/or energy estimates for the application.Type: ApplicationFiled: July 15, 2002Publication date: January 15, 2004Inventors: Gerard Chauvel, Dominique D'Inverno, Serge Lasserre, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Frederic Parain, Jean-Paul Routeau
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Publication number: 20030217090Abstract: A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.Type: ApplicationFiled: May 20, 2002Publication date: November 20, 2003Inventors: Gerard Chauvel, Dominique D'Inverno, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Frederic Parain, Jean-Paul Routeau, Salam Majoul
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Publication number: 20030079213Abstract: A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code modules from a plurality of available program code modules in accordance with said desired program code characteristic, and generating program code for translating high level code into instructions for said target processor from said selected one or more predefined program code modules. Preferably, the method comprises forming agglomerated program code from a plurality of program code modules in accordance with said desired program code characteristic.Type: ApplicationFiled: October 24, 2001Publication date: April 24, 2003Inventors: Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Gerard Chauvel, Dominique D'Inverno, Teresa Higuera, Valerie Issarny, Serge Lasserre, Frederic Parain, Jean-Paul Routeau