Patents by Inventor Frederic Reblewski
Frederic Reblewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8346530Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.Type: GrantFiled: October 26, 2009Date of Patent: January 1, 2013Assignee: Mentor Graphics CorporationInventor: Frederic Reblewski
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Patent number: 8010826Abstract: Reconfigurable circuits, methods, and systems with reconfigurable interconnect devices, clusters of reconfigurable logic devices, and a programming interface configured to receive configuration data to configure a first combination of the reconfigurable interconnect and logic devices to implement a circuit, and to remap a portion of the received configuration data, corresponding to a defective cluster, from the defective cluster to another non-defective cluster of the plurality of clusters to configure a second combination of the reconfigurable interconnect and logic devices to implement the circuit.Type: GrantFiled: November 11, 2009Date of Patent: August 30, 2011Assignee: Meta SystemsInventors: Frédéric Réblewski, Olivier V. LePape
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Patent number: 8003906Abstract: Embodiments of crossbar devices constructed with Micro-Electro-Mechanical Systems (MEMS) switches are disclosed herein. A crossbar device may comprise m input terminals, n output terminals, n control lines and m×n MEMS switches coupled to the n control lines to selectively couple the m input terminals to the n output terminal. Each of the MEMS switches may comprise a contact node coupled to one of the m input terminals, a cantilever coupled to one of the n output terminals, a control node coupled to one of the n control lines to electrostatically control the cantilever to contact the contact node or be away from the contact node using electrostatic attractive or repulsive force respectively. The cantilever and the contact node are configured to remain in contact by molecular adhesion force, after the cantilever has been electrostatically controlled to contact the contact node, and the electrostatic attractive force has been removed. Other embodiments may be described and claimed.Type: GrantFiled: October 31, 2008Date of Patent: August 23, 2011Assignee: Meta SystemsInventors: Carl Ebeling, Frederic Reblewski, Olivier V. Lepape, Jean Barbier
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Patent number: 7924845Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.Type: GrantFiled: September 30, 2003Date of Patent: April 12, 2011Assignee: Mentor Graphics CorporationInventors: Philippe Diehl, Marc Vieillot, Cyril Quennesson, Gilles Laurent, Frederic Reblewski
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Publication number: 20100108479Abstract: Embodiments of crossbar devices constructed with Micro-Electro-Mechanical Systems (MEMS) switches are disclosed herein. A crossbar device may comprise m input terminals, n output terminals, n control lines and m×n MEMS switches coupled to the n control lines to selectively couple the m input terminals to the n output terminal. Each of the MEMS switches may comprise a contact node coupled to one of the m input terminals, a cantilever coupled to one of the n output terminals, a control node coupled to one of the n control lines to electrostatically control the cantilever to contact the contact node or be away from the contact node using electrostatic attractive or repulsive force respectively. The cantilever and the contact node are configured to remain in contact by molecular adhesion force, after the cantilever has been electrostatically controlled to contact the contact node, and the electrostatic attractive force has been removed. Other embodiments may be described and claimed.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: M2000Inventors: Carl Ebeling, Frederic Reblewski, Olivier V. Lepape, Jean Barbier
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Publication number: 20100095147Abstract: Reconfigurable circuits, methods, and systems with reconfigurable interconnect devices, clusters of reconfigurable logic devices, and a programming interface configured to receive configuration data to configure a first combination of the reconfigurable interconnect and logic devices to implement a circuit, and to remap a portion of the received configuration data, corresponding to a defective cluster, from the defective cluster to another non-defective cluster of the plurality of clusters to configure a second combination of the reconfigurable interconnect and logic devices to implement the circuit.Type: ApplicationFiled: November 11, 2009Publication date: April 15, 2010Applicant: Abound Logic, S.A.S.Inventors: Frédéric Réblewski, Olivier V. LePape
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Patent number: 7698118Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.Type: GrantFiled: April 15, 2004Date of Patent: April 13, 2010Assignee: Mentor Graphics CorporationInventor: Frederic Reblewski
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Publication number: 20100057426Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.Type: ApplicationFiled: October 26, 2009Publication date: March 4, 2010Applicant: MENTOR GRAPHICS CORPORATIONInventor: Frederic Reblewski
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Patent number: 7568136Abstract: Reconfigurable circuits and systems having a recovery module coupled to the reconfigurable circuit and configured to access the configuration memory to retrieve configuration data stored in the configuration memory. The recovery module analyzes the retrieved configuration data to determine whether the configuration data has been corrupted and, if so, restores the configuration data to their uncorrupted state. Methods of operating such reconfigurable circuits and systems are also described.Type: GrantFiled: November 8, 2005Date of Patent: July 28, 2009Assignee: M2000 SA.Inventors: Frédéric Réblewski, Olivier V. Lepape
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Patent number: 7568064Abstract: A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.Type: GrantFiled: February 21, 2006Date of Patent: July 28, 2009Assignee: M2000Inventors: Frédéric Réblewski, César Douady
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Publication number: 20090177912Abstract: A reconfigurable circuit having redundant reconfigurable clusters is described herein.Type: ApplicationFiled: December 9, 2008Publication date: July 9, 2009Applicant: M2000Inventor: Frederic Reblewski
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Patent number: 7529998Abstract: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.Type: GrantFiled: August 17, 2007Date of Patent: May 5, 2009Assignee: M2000 SA.Inventor: Frédéric Réblewski
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Patent number: 7480610Abstract: A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.Type: GrantFiled: July 12, 2005Date of Patent: January 20, 2009Assignee: Mentor Graphics CorporationInventors: David C. Scott, Charles W. Selvidge, Joshua D. Marantz, Frédéric Reblewski
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Patent number: 7478261Abstract: A reconfigurable circuit having redundant reconfigurable clusters is described herein.Type: GrantFiled: September 13, 2005Date of Patent: January 13, 2009Assignee: M2000Inventor: Frédéric Réblewski
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Publication number: 20070283190Abstract: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.Type: ApplicationFiled: August 17, 2007Publication date: December 6, 2007Applicant: M2000 SA.Inventor: Frederic Reblewski
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Patent number: 7305633Abstract: Data processing resources are distributively provided to an emulation system to locally and correspondingly configure emulation integrated circuits. In certain embodiments the data processing resources also perform emulation functions. In one embodiment, the distributed data processing resources are disposed on logic boards having emulation ICs that include the reconfigurable logic resources. In another embodiment, data processing resources receive commands transmitted from a workstation executing electronic design automation (EDA) software. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs. The board and IC disposed distributed data processing resources cooperatively perform the configuration and emulation functions as described.Type: GrantFiled: December 17, 2003Date of Patent: December 4, 2007Assignee: Mentor Graphics CorporationInventors: Frederic Josso, Xavier Montagne, Frederic Reblewski
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Patent number: 7286976Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.Type: GrantFiled: June 10, 2003Date of Patent: October 23, 2007Assignee: Mentor Graphics (Holding) Ltd.Inventors: Philippe Diehl, Gilles Laurent, Frederic Reblewski
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Patent number: 7275196Abstract: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.Type: GrantFiled: November 23, 2005Date of Patent: September 25, 2007Assignee: M2000 S.A.Inventor: Frédéric Réblewski
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Patent number: 7263456Abstract: Reconfigurable circuits with configuration data loaders are described herein. The configuration data loaders are adapted to enable on circuit finalization of configuration data provided in symbolic form, not fully resolved.Type: GrantFiled: January 10, 2006Date of Patent: August 28, 2007Assignee: M2000Inventor: Frédéric Réblewski
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Publication number: 20070194807Abstract: A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.Type: ApplicationFiled: February 21, 2006Publication date: August 23, 2007Inventors: Frederic Reblewski, Cesar Douady