Patents by Inventor Frederick A. Ware

Frederick A. Ware has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210326286
    Abstract: An integrated circuit including control/configure circuitry which interfaces with a plurality of interconnected (e.g., serially) multiplier-accumulator circuits and/or one or more rows of interconnected (e.g., serially) multiplier-accumulator circuits. The control/configure circuitry may include a plurality of control/configure circuits, each control/configure circuit interfaces with at least one multi-bit MAC execution pipeline, wherein each pipeline includes a plurality of interconnected (e.g., serially) multiplier-accumulator circuits. Each control/configure circuit may include one or more (or all) of (i) a configurable input data signal path to provide data to the MACs of the pipeline during the execution sequence(s), (ii) a configurable accumulation data path for the ongoing/accumulating MAC accumulation totals generated by the MACs during an execution sequence, and (iii) a configurable output data path for the output data generated by execution sequence (i.e.
    Type: Application
    Filed: March 25, 2021
    Publication date: October 21, 2021
    Applicant: Flex Logix Technologies, Inc.
    Inventors: Frederick A. Ware, Cheng C. Wang
  • Publication number: 20210326204
    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
    Type: Application
    Filed: November 30, 2020
    Publication date: October 21, 2021
    Inventors: Frederick A. WARE, Brent S. HAUKNESS, Lawrence LAI
  • Publication number: 20210318969
    Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 14, 2021
    Inventors: Frederick A. Ware, Craig E. Hampel
  • Patent number: 11146269
    Abstract: An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Carl W. Werner
  • Publication number: 20210303383
    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
    Type: Application
    Filed: April 21, 2021
    Publication date: September 30, 2021
    Inventors: Thomas J. GIOVANNINI, Catherine CHEN, Scott C. BEST, John Eric LINSTADT, Frederick A. WARE
  • Patent number: 11133843
    Abstract: An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 28, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Carl W. Werner
  • Patent number: 11132307
    Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Publication number: 20210294531
    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.
    Type: Application
    Filed: April 20, 2021
    Publication date: September 23, 2021
    Inventors: Frederick A. Ware, Scott C. Best
  • Publication number: 20210280226
    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 9, 2021
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 11115179
    Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: September 7, 2021
    Assignee: Rambus Inc.
    Inventors: Bret G. Stott, Craig E. Hampel, Frederick A. Ware
  • Patent number: 11109512
    Abstract: The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 31, 2021
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
  • Patent number: 11108510
    Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: August 31, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Richard E. Perego, Craig E. Hampel
  • Patent number: 11100976
    Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 24, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Publication number: 20210248031
    Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.
    Type: Application
    Filed: June 14, 2019
    Publication date: August 12, 2021
    Inventors: Angus William McLAREN, Robert A. HEATON, Aaron ALI, Frederick A. WARE
  • Publication number: 20210241844
    Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
    Type: Application
    Filed: March 20, 2019
    Publication date: August 5, 2021
    Inventors: John Eric LINSTADT, Frederick A. WARE
  • Patent number: 11080185
    Abstract: A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 3, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Publication number: 20210232203
    Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.
    Type: Application
    Filed: December 10, 2020
    Publication date: July 29, 2021
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
  • Publication number: 20210233599
    Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 29, 2021
    Inventors: Thomas Vogelsang, William Ng, Frederick A. Ware
  • Patent number: 11075671
    Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 27, 2021
    Assignee: Rambus Inc.
    Inventors: John W. Poulton, Frederick A. Ware, Carl W. Werner
  • Patent number: 11069392
    Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: July 20, 2021
    Assignee: Rambus, Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang