Abstract: An imaging device includes a plurality of unit pixels or pixels, with each pixel separated from every other unit pixel by an isolation structure. Each unit pixel includes a photoelectric conversion unit, a pixel imaging signal readout circuit, and an address event detection readout circuit. A first transfer transistor selectively connects the photoelectric conversion unit to the pixel imaging signal readout circuit, and a second transfer transistor selectively connects the photoelectric conversion unit to the address event detection readout circuit. The photoelectric conversion unit, the pixel imaging signal readout circuit, the address event detection readout circuit, and the first and second transfer transistors for a given pixel are located within a pixel area defined by the isolation structure. The isolation structure may be in the form of a full thickness dielectric trench isolation structure.

Abstract: An imaging device includes a plurality of unit pixels disposed into pixel groups that are separated from one another by isolation structures. Unit pixels within each pixel group are separated from one another by isolation structures and share circuit elements. The isolation structures between pixel groups are full thickness isolation structures. At least a portion of the isolation structures between unit pixels within a pixel group are deep trench isolation structures.

Abstract: An imaging device includes a first pixel. The first pixel includes a first photoelectric conversion region disposed in a first substrate and that converts incident light into first electric charges. The first pixel includes a first readout circuit including a first converter that converts the first electric charges into a first logarithmic voltage signal. The imaging device includes at least one bonding pad on the first substrate and in electrical contact with the first converter. The at least one bonding pad overlaps at least part of the first pixel.

Abstract: A light receiving element includes: a first tap; a second tap; a first photoelectric conversion unit configured to detect a charge generated by photoelectric conversion according to a light amount of incident light in accordance with a voltage applied to the first tap; a second photoelectric conversion unit configured to detect a charge generated by photoelectric conversion according to a light amount of the incident light in accordance with a voltage applied to the second tap; a plurality of accumulation units configured to accumulate the charges generated by the first photoelectric conversion unit and the second photoelectric conversion unit; a plurality of transmission units configured to transmit the charges generated by the first photoelectric conversion unit and the second photoelectric conversion unit to the plurality of accumulation units; and a calculation unit configured to execute calculation based on the charges accumulated in the plurality of accumulation units.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Abstract: An imaging apparatus with logarithmic characteristics includes: a photodiode that receives light; a well tap unit that fixes the potential of an N-type region of the photodiode; and a resetting unit that resets the photodiode, a P-type region of the photodiode outputting a voltage signal equivalent to a photocurrent subjected to logarithmic compression. The first potential to be supplied to the well tap unit is made lower than the second potential to be supplied to the resetting unit, so that the capacitance formed with the PN junction of the photodiode is charged when the resetting unit performs a reset operation. The present technology can be applied to unit pixels having logarithmic characteristics.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Abstract: An imaging apparatus with logarithmic characteristics includes: a photodiode that receives light; a well tap unit that fixes the potential of an N-type region of the photodiode; and a resetting unit that resets the photodiode, a P-type region of the photodiode outputting a voltage signal equivalent to a photocurrent subjected to logarithmic compression. The first potential to be supplied to the well tap unit is made lower than the second potential to be supplied to the resetting unit, so that the capacitance formed with the PN junction of the photodiode is charged when the resetting unit performs a reset operation. The present technology can be applied to unit pixels having logarithmic characteristics.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Abstract: An image sensor includes a pixel circuit that includes a light sensing element and a charge storage node formed in a substrate, an output element having a control electrode formed in an electrode layer above the substrate, the output element generating an output signal corresponding to charge generated by the light sensing element and held by the charge storage node, and a local metal interconnect that electrically connects the charge storage node to the control electrode. Control wirings that control operations of the pixel circuit are formed in wiring layers that are located above the electrode layer. The metal interconnect is formed in a layer that is located above the electrode layer and below a lowest one of the wiring layers such that a given one of the control wirings overlaps the metal interconnect so as to form a parallel plate capacitor in a region of overlap.

Abstract: Systems, methods, and devices of the various embodiments enable cartonization of products for store replenishment based on the individual store layout of each store of a group of stores to which the cartonized products are to be provided.

Abstract: An image sensor includes a pixel circuit that includes a light sensing element and a charge storage node formed in a substrate, an output element having a control electrode formed in an electrode layer above the substrate, the output element generating an output signal corresponding to charge generated by the light sensing element and held by the charge storage node, and a local metal interconnect that electrically connects the charge storage node to the control electrode. Control wirings that control operations of the pixel circuit are formed in wiring layers that are located above the electrode layer. The metal interconnect is formed in a layer that is located above the electrode layer and below a lowest one of the wiring layers such that a given one of the control wirings overlaps the metal interconnect so as to form a parallel plate capacitor in a region of overlap.

Abstract: The cartonization process in a distribution center can be modified to account for factors which influence the efficiency with which the products distributed from the distribution center can be stocked onto store shelves, such as layout (i.e., planogram) information indicating where the various products will actually be located in a store.

Abstract: Systems, methods, and devices of the various embodiments enable cartonization of products for store replenishment based on the individual store layout of each store of a group of stores to which the cartonized products are to be provided.

Abstract: An enhanced shallow trench isolation method for fabricating radiation tolerant integrated circuit devices is disclosed. A layer of pad oxide is first deposited on a semiconductor substrate. A layer of pad nitride is then deposited on the pad oxide layer. A trench is defined within the semiconductor substrate by selectively etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate. Boron ions are then implanted into both the bottom and along the sidewalls of the trench. Subsequently, a trench plug is formed within the trench by depositing an insulating material into the trench and by removing an excess portion of the insulating material. A p-well is implanted to a depth just below the depth of the bottom of the trench. This helps to keep the threshold voltage of the IC device below the trench at a high level, and thereby keep post-radiation leakage low. Then, an electrically neutral species is implanted into the wafer.

Abstract: The cartonization process in a distribution center can be modified to account for factors which influence the efficiency with which the products distributed from the distribution center can be stocked onto store shelves, such as layout (i.e., planogram) information indicating where the various products will actually be located in a store.

Abstract: A structure and method for fabricating imagers that detect light from the backside of the wafer. The structure may have less complex focusing, reduced crosstalk, tighter pixel packing density, increased quantum efficiency, and wafer-level packaging. The fabrication of the imager includes forming an imaging device on a silicon wafer, adhering an interconnect wafer to the device wafer, forming interconnects on the interconnect wafer, etching away the substrate of the device wafer, and patterning additional layers such as nitrides, color filter arrays, and lenses on the backside of the device wafer.

Abstract: In some embodiments, global climate change is mitigated by increasing Earth's surface albedo. In some embodiments, a naturally occurring, reflective crystalline material can applied over vast surface areas to provide a durable reflective layer of such material, thereby amplifying the Earth's albedo.

Abstract: A method, apparatus, and system that provides one or more charge collecting protection regions in a pixel array, each formed below a storage region of a pixel cell, but not below at least one photosensor of one pixel of the array. The storage region includes a floating diffusion region and/or a storage gate in the pixel cell of the imaging device. The protection regions can keep stray charges from reaching the storage regions.