Abstract: Methods, systems, apparatus and computer-readable media are disclosed for translating human-readable software elements into a machine executable format. According to a first aspect, a method is disclosed for translating human-readable software elements into a machine executable format. The method includes defining a plurality of actions to be performed. Each action is associated with at least one human-readable software element, and each action having an associated element type selected from among a plurality of element types. The method also includes sequencing the plurality of actions according to the plurality of associated element types. The method further includes executing a plurality of asynchronous action processing tasks, and assigning an action to each of the asynchronous action processing tasks in accordance with the sequencing until each of the actions is performed.

Abstract: Methods, systems, apparatus and computer-readable media are disclosed for generating extract files. A first example method is disclosed for generating an extract file. The method includes receiving a data request and analyzing the data request to identify at least one record of at least one file containing data associated with the data request. The method also includes extracting the identified records and formatting the identified records according to a comma separated value format. The method further includes outputting an extract file containing the formatted records. Other methods, apparatus, systems and computer readable media are disclosed for generating extract files.

Abstract: Disclosed is an extender sublayer device comprising an MII to transmit data between the MII and a plurality of data lanes in an AUI. The extender sublayer device comprises a plurality of internal device pins and a plurality of external device pins where at least some of the external device pins are associated with data lanes in the AUI. Logic may selectively couple the one or more internal circuit pins to one of the external device pins in response to an external control signal.

Abstract: A bandgap voltage reference circuit and related method characterized in having a first current source for generating a first current having a positive temperature coefficient, a second current source for generating a second current having a negative temperature coefficient, and a resistive element to receive both the first and second current to develop a reference voltage. By configuring the circuit such that the magnitudes of the positive and negative temperature coefficients are substantially the same, the reference voltage becomes substantially invariant with changes in temperature. Another circuit is provided in conjunction with the voltage reference circuit to substantially equalize the drain-to-source voltage of the transistors used in the voltage reference circuit.

Abstract: A bandgap voltage reference circuit and related method characterized in having a first current source for generating a first current having a positive temperature coefficient, a second current source for generating a second current having a negative temperature coefficient, and a resistive element to receive both the first and second current to develop a reference voltage. By configuring the circuit such that the magnitudes of the positive and negative temperature coefficients are substantially the same, the reference voltage becomes substantially invariant with changes in temperature. Another circuit is provided in conjunction with the voltage reference circuit to substantially equalize the drain-to-source voltage of the transistors used in the voltage reference circuit.

Abstract: A bi-planar multi-chip package has die mounted on both sides of an insulating flexible carrier. The die are located in two parallel planes, with the flexible carrier located on a third plane between the two die planes. The die are mounted with the active circuit area facing each other on opposing sides of the flexible carrier. The carrier has conductive layers forming interconnect traces on both sides, and through-vias for connecting traces on opposite sides. The opposing die are mounted to the carrier with a solder-bump process with opposing pads located directly opposite each other. Vias are located in close proximity to the pads, between adjacent pads on the flexible carrier. Because the vias are between two adjacent pads, the interconnect length between two pads is on the order of the pad pitch. Thus opposing pads on the two die may be connected through the adjacent via with a small interconnect length.

Abstract: A static RAM memory is ideally suited for BiCMOS processes. As in standard CMOS memory cells, the cells have cross-coupled inverters that have more efficient n-channel transistors for the drive transistors, which pull a bit line low during a read operation. The weaker p-channel transistors are used for load transistors in the cross-coupled inverters, adding to cell stability while requiring no power. In contrast to prior-art cells, p-channel pass transistors are used. Common-emitter word-line drivers are also used that require a small input-voltage swing in comparison with the large word-line voltage swing. A low voltage on the word line selects a memory cell by causing p-channel pass transistors to conduct, coupling bit lines to the cross-coupled inverters in the memory cell. Power consumption is reduced since only one selected word line is at a low voltage, while the deselected word lines are at a high voltage.

Abstract: A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor, to which this application is directed to, as the shunt feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.

Abstract: A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.

Abstract: A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.

Abstract: A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.