Abstract: A mechanism for verifying system behavior includes: (1) A “constraint-based inference engine” and (2) a “constraint-based simulator.” The inference engine accepts logical/temporal/data dependencies describing a system implementation and automatically derives new logical/temporal/data dependencies describing the input/output (“black-box”) behavior of the system or other aspect of the system's behavior. This capability means that a “behavioral model” can be automatically extracted from a “structural model,” thereby supporting “encapsulation” and “information hiding.

Abstract: An apparatus and method for verifying system behavior using behavior-constraint-calculus analysis is disclosed. The apparatus accepts a first “known” constraint graph and a second “conjectured” constraint graph. The apparatus transforms the second graph in such a way that the resultant “verified” graph “accepts” only those paths that are implied by the first graph and appear in the second graph.

Abstract: A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of reset lines which include main reset lines, column reset lines, and sector reset lines. Each of the main reset lines receives a different reset signal. Each of the column reset lines is associated with a particular column of logic cells of the matrix. Each column reset line is selectively connectable to any one of the main reset lines to receive a selected reset signal. Each of the sector reset lines is connected to a subset of the logic cells in a column. The column reset lines are selective connectable to the logic cells in this respective associated columns by means of the sector reset lines that are connectable to the column reset lines.

Abstract: A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of clock lines which include main clock lines, column clock lines, and sector clock lines. Each of the main clock lines receives a different clock signal. Each of the column clock lines is associated with a particular column of logic cells of the matrix. Each column clock line is selectively connectable to any one of the main clock lines to receive a selected clock signal. Each of the sector clock lines is connected to a subset of the logic cells in a column. The column clock lines are selective connectable to the logic cells in this respective associated columns by means of the sector clock lines that are connectable to the column clock lines. A circuit for selectively inverting clock signals may be located along each sector clock line.

Abstract: A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces.

Abstract: A field programmable gate array (FPGA) comprising a matrix of programmable logic cells, a bus network of local and express bus lines, and a system of perimeter I/O pads is disclosed. Logic cells are directly connected to neighboring nearest cells, including diagonally and orthogonally adjacent cells, and are also connected to local bus lines. Such direct cell-to-cell connections allow both directions of signal propagation. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, I/O pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.

Abstract: A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces.

Abstract: A method and apparatus for generating a sequence of displacement vectors and associated minimal error values. The vectors and associated values represent the best match of a current block of elements of a first frame of a signal with one of a plurality of search blocks of elements located within a corresponding search window of a second frame. A first stream of data, representing the elements of the first frame is transmitted to a linear array of processing units; a second stream of data, representing the elements of the second frame is transmitted to the array; a hybrid stream of data from the elements of the second stream is synthesized such that the elements of the hybrid stream are aligned in time with the elements of the first stream so as to enable each processing unit of the array to compute an error between a particular current block and a different search block of the corresponding search window. The error is a measure of the difference between two blocks of elements.

Abstract: A method and apparatus for generating a sequence of displacement vectors and associated minimal error values. The vectors and-associated values represent the best match of a current block of elements of a first frame of a signal with one of a plurality of search blocks of elements located within a corresponding search window of a second frame. A first stream of data, representing the elements of the first frame is transmitted to a linear array of processing units; a second stream of data, representing the elements of the second frame is transmitted to the array; a hybrid stream of data from the elements of the second stream is synthesized such that the elements of the hybrid stream are aligned in time with the elements of the first stream so as to enable each processing unit of the array to compute an error between a particular current block and a different search block of the corresponding search window. The error is a measure of the difference between two blocks of elements.

Abstract: An improved programmable logic cell for use in a programmable logic array comprising cells which are arranged in a two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), and one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell receives input(s) from each of its nearest neighbors and additional input(s) (from a bus, pin, or neighbor) and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell comprises two upstream gates, the outputs of which feed two downstream gates, one of which is an exclusive-OR gate which feeds a downstream register.

Abstract: A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Abstract: A logic cell is described having four inputs, four outputs, a control store, means for multiplexing the four inputs onto two leads and logic means that operate in response to the signals on the two leads and signals from the control store to produce output signals which are applied to the four outputs. Illustrative logic functions provided by the logic means include a cross-over or identify function, a change in the routing direction of an input signal, NAND and XOR gates and a D-type flip-flop. The selection of two of the four inputs as well as the selection of the particular logic function that is implemented is controlled by control bits stored in the control store. Numerous such logic cells are arranged in a two-dimensional matrix such that each cell has four nearest neighbor cells, one to its left (or to the West) one to its right (or to the East), one above it (or to the North) and one below it (or to the South).

Abstract: A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Abstract: Programmable logic cells, and arrays of those cells, having certain characteristics, including: (1) the ability to program each cell to act either as a logic element or as a logical identity element(s) between one or more inputs and one or more outputs; (2) the ability to rotate circuits by 90.degree. and to reflect circuits about horizontal and vertical axes; (3) an integrated logic and communication structure which emphasizes strictly local communications; (4) a minimal complexity of logic functions available at the cell level, making available a very fine-grained logic structure; and (5) suitability for implementation of both synchronous and asynchronous logic, including speed-independent circuits. Cells are arranged in a grid, with each cell communicating with its north, east, west and south neighbors. The cells are programmable to several states.

Abstract: A logic cell is described having four inputs, four outputs, a control store, means for multiplexing the four inputs onto two leads and logic means that operate in response to the signals on the two leads and signals from the control store to product output signals which are applied to the four outputs. Illustrative logic functions provided by the logic means include a cross-over or identity function, a change in the routing direction of an input signal, NAND and XOR gates and a D-type flip-flop. The selection of two of the four inputs as well as the selection of the particular logic function that is implemented is controlled by control bits stored in the control store. Numerous such logic cells are arranged in a two-dimensional matrix such that each cell has four nearest neighbor cells, one to its left (or to the West) one to its right (or to the East), one above it (or to the North) and one below it (or to the South).

Abstract: Programmable logic cells, and arrays of those cells, having certain characteristics, including: (1) the ability to program each cell to act either as a logic element or as a logical identity element(s) between one or more inputs and one or more outputs; (2) the ability to rotate circuits by 90.degree. and to reflect circuits about horizontal and vertical axes; (3) an integrated logic and communication structure which emphasizes strictly local communications; (4) a minimal complexity of logic functions available at the cell level, making available a very fine-grained logic structure; and (5) suitability for implementation of both synchronous and asynchronous logic, including speed-independent circuits. Cells are arranged in a grid, with each cell communicating with its north, east, west and south neighbors. The cells are programmable to several states.

Abstract: A system for programming an asynchronous logic cell and a two- or three-dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The programming system facilitates the construction of circuits, circuit modules, black box elements and the like, with provision for storing such building blocks in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together.

Abstract: An asynchronous logic cell and a two- or three dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The array can be used to implement any circuit capable of being modelled as a broad class of Petri Nets. Configurations for (i.e., programs for setting cell switches to create) circuit blocks such as adders, multiplexers, buffer stacks, and so forth, may be stored in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together.