Abstract: A locked-loop circuit includes phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase. Sampling circuitry sequentially samples the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock. Edge detection logic accumulates phase information from the multiple sampling clocks and determines, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock. Index logic generates index values for any of the determined early edge detection signals. The index logic transfers the generated index values to a master phase transfer logic unit. Phase adjust logic adjusts the master clock phase based on a selected one of the generated index values.

Abstract: A locked-loop circuit includes phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase. Sampling circuitry sequentially samples the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock. Edge detection logic accumulates phase information from the multiple sampling clocks and determines, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock. Index logic generates index values for any of the determined early edge detection signals, each index value corresponding to a phase difference between the master sampling clock phase and a given sampling clock phase associated with a corresponding early edge detection signal. The index logic transfers the generated index values to a master phase transfer logic unit.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.

Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.

Abstract: A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep secondary cache memory (SCM), each with multiple banks to access data simultaneously. A dedicated pre-fetching logic is used to obtain pixel data from an external memory upon receiving control parameters from an external processor system (PU1), and to store that data in the PCM based on a secondary control queue. The data are then prepared in specific block sizes and in specific format, and then stored in the PCM based on optimally sized pre-fetching primary control queue. The prepared data are then read by another external processor system (PU2) for processing. The cache control logic ensures the coherency of data and control parameters at the input of the PU2.

Abstract: An image data processing method and system receives image data from a burst memory buffer and provides output image data to a vertical filter for filtering. The method determines whether a new frame of input image data has been received, said frame of data having a plurality of blocks, each block having a plurality of rows and columns. A vertical input buffer uses a read pointer, an oldest unused data pointer, and a write pointer to keep track of the data that is being read and stored. Data is read and stored into said vertical input buffer by determining the minimum offset for the block, reading a row of input image data from the burst memory buffer and skipping the row depending on the minimum offset until minimum offset reached, and storing the row of input image data in said vertical input buffer for processing by the vertical filter until the buffer is full. If the entire frame has been processed then the pointers are all reset.

Abstract: An image data processing method and system receives image data from a burst memory buffer and provides output image data to a vertical filter for filtering. The method determines whether a new frame of input image data has been received, said frame of data having a plurality of blocks, each block having a plurality of rows and columns. A vertical input buffer uses a read pointer, an oldest unused data pointer, and a write pointer to keep track of the data that is being read and stored. Data is read and stored into said vertical input buffer by determining the minimum offset for the block, reading a row of input image data from the burst memory buffer and skipping the row depending on the minimum offset until minimum offset reached, and storing the row of input image data in said vertical input buffer for processing by the vertical filter until the buffer is full. If the entire frame has been processed then the pointers are all reset.