Patents by Inventor Frederick E. Beville

Frederick E. Beville has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11749576
    Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 5, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: John D. Brazzle, Frederick E. Beville, David R. Ng, Michael J. Anderson, Yucheng Ying
  • Patent number: 11410977
    Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 9, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: John D. Brazzle, Frederick E. Beville, Yucheng Ying, Zafer S. Kutlu
  • Patent number: 11272618
    Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 8, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: John David Brazzle, Frederick E. Beville, David A. Pruitt
  • Publication number: 20210111084
    Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 15, 2021
    Inventors: John D. Brazzle, Frederick E. Beville, David R. Ng, Michael J. Anderson, Yucheng Ying
  • Publication number: 20200152614
    Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 14, 2020
    Inventors: John D. Brazzle, Frederick E. Beville, Yucheng Ying, Zafer S. Kutlu
  • Patent number: 10497635
    Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 3, 2019
    Assignee: Linear Technology Holding LLC
    Inventors: John D. Brazzle, Frederick E. Beville, David R. Ng, Michael J. Anderson, Yucheng Ying
  • Publication number: 20190304865
    Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.
    Type: Application
    Filed: October 4, 2018
    Publication date: October 3, 2019
    Inventors: John D. Brazzle, Frederick E. Beville, David R. Ng, Michael J. Anderson, Yucheng Ying
  • Publication number: 20190141834
    Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module. A method of making a component-on-package circuit may include attaching a component for an electrical circuit to a circuit module. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component after the attachment both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides a spring-like cushioning of force applied to the component in the direction of the circuit module.
    Type: Application
    Filed: April 11, 2017
    Publication date: May 9, 2019
    Inventors: John David Brazzle, Frederick E. Beville, David A. Pruitt
  • Publication number: 20170311447
    Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module. A method of making a component-on-package circuit may include attaching a component for an electrical circuit to a circuit module. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component after the attachment both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides a spring-like cushioning of force applied to the component in the direction of the circuit module.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 26, 2017
    Inventors: John David BRAZZLE, Frederick E. BEVILLE, David A. PRUITT
  • Patent number: 8163643
    Abstract: A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: April 24, 2012
    Assignee: Linear Technology Corporation
    Inventors: Maurice O. Othieno, Ramaswamy Ranganathan, Frederick E. Beville, David A. Pruitt, William D. Griffitts