Abstract: The disclosure provides a hardware monitor device connectable to a large high speed processor (in a uniprocessor or multiprocessor system) to correlate software activity to hardware activity by capturing samples of instruction addresses (which are architecturally visable to the software) that cause the occurrence of the monitored activity manifested by electrical signals in processor circuit (e.g. setting of a latch), and recording the instruction addresses with a designation of the monitored event(s) (e.g. a DLAT reference or cache misses). The embodiment samples which instructions are to be captured by selecting one per N number of samplings of a specified event to be monitored.