Patents by Inventor Frederick Furtek

Frederick Furtek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060167664
    Abstract: A mechanism for verifying system behavior includes: (1) A “constraint-based inference engine” and (2) a “constraint-based simulator.” The inference engine accepts logical/temporal/data dependencies describing a system implementation and automatically derives new logical/temporal/data dependencies describing the input/output (“black-box”) behavior of the system or other aspect of the system's behavior. This capability means that a “behavioral model” can be automatically extracted from a “structural model,” thereby. supporting “encapsulation” and “information hiding.
    Type: Application
    Filed: November 2, 2005
    Publication date: July 27, 2006
    Inventor: Frederick Furtek
  • Patent number: 5298805
    Abstract: A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: March 29, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Tim Garverick, Jim Sutherland, Sanjay Popli, Venkata Alturi, Arthur Smith, Jr., Scott Pickett, David Hawley, Shao-Pin Chen, Shankar Moni, Benjamin S. Ting, Rafael C. Camarota, Shin-Mann Day, Frederick Furtek
  • Patent number: 5296759
    Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. Adjacent abutting cells logic cells are interconnectable via horizontal and vertical configurable interconnections running between adjacent cells. Furthermore, configurable diagonal interconnections run between diagonally adjacent abutting logic cells in the array.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: March 22, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Jim Sutherland, Sanjay Popli, Venkata Alturi, Frederick Furtek