Abstract: Aspects of a method and system for hierarchical motion estimation with multi-layer sub-pixel accuracy and motion vector smoothing are presented. Aspects of the system may include hierarchical motion vector computation that enables motion vectors to be computed at each level in the hierarchy based on a distinct pixel resolution level. A smoothing algorithm may be utilized to suppress spurious motion vector generation. The motion vectors computed at one level in the hierarchy may be utilized when computing motion vectors in a subsequent level. A bias value may be computed for each motion vector that provides an evaluation metric that may enable determination of whether the computed motion vector is to be utilized to enable generation of the interpolated image frame.

Abstract: Systems and method for processing v-chip data for an MPEG-2 decoder with personal video recording functionality are provided. In one example, a system that processes V-Chip data with personal video recording functionality may include a data transport engine and a video decoder. The video decoder may be coupled to the data transport engine and may be adapted to parse out V-Chip data.

Abstract: Aspects of a method and system for hierarchical motion estimation with multi-layer sub-pixel accuracy and motion vector smoothing are presented. Aspects of the system may include hierarchical motion vector computation that enables motion vectors to be computed at each level in the hierarchy based on a distinct pixel resolution level. A smoothing algorithm may be utilized to suppress spurious motion vector generation. The motion vectors computed at one level in the hierarchy may be utilized when computing motion vectors in a subsequent level. A bias value may be computed for each motion vector that provides an evaluation metric that may enable determination of whether the computed motion vector is to be utilized to enable generation of the interpolated image frame.

Abstract: System and methods for processing signals in a television system are disclosed and may include measuring relative power of RF carriers over a full bandwidth of one or more received TV channels. The method may also include determining based on the measured relative power, whether the one or more received TV channels includes a digital component or an analog component without demodulating the received TV channel. It may be determined whether the one or more received TV channels includes a digital component or an analog component without synchronizing and/or decoding the one or more received TV channels. The method may further include tuning to the one or more received TV channels. It may be determined whether an applied power gain for the one or more received TV channels is a maximum power gain.

Abstract: Aspects of a method and system for motion vector estimation using a pivotal pixel search are presented. Aspects of the system may include an image interpolation system that enables selection of an interpolated picture element neighborhood within an interpolated image frame. The image interpolation system may enable selection of one of a plurality of computed candidate motion vectors based on the location of the interpolated picture element neighborhood within the interpolated image frame. The image interpolation system may enable generation of picture element values within the selected interpolated picture element neighborhood based on at least the selected one of the plurality of computed candidate motion vectors.

Abstract: Aspects of a method and system for hierarchical motion estimation with multi-layer sub-pixel accuracy and motion vector smoothing are presented. Aspects of the system may include hierarchical motion vector computation that enables motion vectors to be computed at each level in the hierarchy based on a distinct pixel resolution level. A smoothing algorithm may be utilized to suppress spurious motion vector generation. The motion vectors computed at one level in the hierarchy may be utilized when computing motion vectors in a subsequent level. A bias value may be computed for each motion vector that provides an evaluation metric that may enable determination of whether the computed motion vector is to be utilized to enable generation of the interpolated image frame.

Abstract: Systems and method for processing v-chip data for an MPEG-2 decoder with personal video recording functionality are provided. In one example, a system that processes V-Chip data with personal video recording functionality may include a data transport engine and a video decoder. The video decoder may be coupled to the data transport engine and may be adapted to parse out V-Chip data.

Abstract: Systems and method for processing v-chip data for an MPEG-2 decoder with personal video recording functionality are provided. In one example, a system that processes V-Chip data with personal video recording functionality may include a data transport engine and a video decoder. The video decoder may be coupled to the data transport engine and may be adapted to parse out V-Chip data.

Abstract: A method and system is provided, which may detect digital QAM, VSB and analog TV signals in a faster and more efficient manner than conventional systems. The system and method may be deployed in, for example, cable TV set-top boxes, cable TV modems and television set receivers, which may be coupled to a cable TV or off-the-air terrestrial network. Power measurements of the RF carriers found in a cable TV channel may be utilized to determine whether a digital QAM signal, digital VSB signal, or an analog signal is present in a TV channel. In this regard, it is not necessary for a receiver to demodulate, lock, synchronize, decode and/or validate any video or audio information or digital bit stream in order to detect digital QAM, digital VSB and analog TV signals, or not signal at all. Accordingly, the process of detecting digital QAM, digital VSB and analog TV signals is shortened and simplified.

Abstract: A method and apparatus for normalizing a score associated with a document is presented. Statistics relating to scores assigned to a set of training documents not relevant to a topic are determined. Scores represent a measure of relevance to the topic. After the various statistics have been collected, a score assigned to a testing document is normalized based on those statistics. The normalized score is then compared to a threshold score. Subsequently, the testing document is designated as relevant or not relevant to the topic based on the comparison.

Abstract: Presented herein are system(s), method(s), and apparatus f or detecting and recovering from false synchronization. When incorrect checksums are encountered, false synchronization and general noisy considerations are distinguished as causes of the incorrect checksums by examining the header data. For example, in one embodiment, a count can be kept and false synchronization and noisy conditions can be distinguished based on the number of detected null packets. In another embodiment, a count of detected PAT packets can be kept, and false synchronization and noisy conditions can be distinguished based on the number of detected PAT packets. In another embodiment, continuity information can be monitored and false synchronization and noisy conditions can be distinguished based on the continuity of the data packets.

Abstract: Presented herein are a system(s), method(s), and apparatus for detecting and recovering from false synchronization. False synchronization can be detected on the fly through either on an interrupt-driven basis or polling-driven basis. The number of incorrect checksums is compared to the number of uncorrectable errors detected. If the number of incorrect checksums is large compared to the number of uncorrectable errors detected, resynchronization occurs.

Abstract: Presented herein are a system(s), method(s), and apparatus for detecting and recovering from false synchronization. False synchronization can be detected on the fly through either on an interrupt-driven basis or polling-driven basis. The number of incorrect checksums is compared to the number of uncorrectable errors detected. If the number of incorrect checksums is large compared to the number of uncorrectable errors detected, resynchronization occurs.

Abstract: Presented herein are a system(s), method(s), and apparatus for detecting and recovering from false synchronization. When incorrect checksums are encountered, false synchronization and general noisy considerations are distinguished as causes of the incorrect checksums by examining the header data. For example, in one embodiment, a count can be kept and false synchronization and noisy conditions can be distinguished based on the number of detected null packets. In another embodiment, a count of detected PAT packets can be kept, and false synchronization and noisy conditions can be distinguished based on the number of detected PAT packets. In another embodiment, continuity information can be monitored and false synchronization and noisy conditions can be distinguished based on the continuity of the data packets.

Abstract: A method and apparatus for normalizing a score associated with a document is presented. Statistics relating to scores assigned to a set of training documents not relevant to a topic arc determined. Scores represent a measure of relevance to the topic. After the various statistics have been collected, a score assigned to a testing document is normalized based on those statistics. The normalized score is then compared to a threshold score. Subsequently, the testing document is designated as relevant or not relevant to the topic based on the comparison.

Abstract: Systems and method for processing v-chip data for an MPEG-2 decoder with personal video recording functionality are provided. In one example, a system that processes V-Chip data with personal video recording functionality may include a data transport engine and a video decoder. The video decoder may be coupled to the data transport engine and may be adapted to parse out V-Chip data.

Abstract: A voltage level shifter with testable cascode devices is disclosed. According to one embodiment, the level shifter includes multiple cascode devices and switches a first output driver according to the values of a data input and an enable input. Testability devices coupled to cascode devices of the level shifter detect a current in response to failure of the corresponding cascode device.

Abstract: A fail-safe Input/Output buffer bias circuit for digital CMOS chips provides protection for Input/Output buffers which have high voltages applied to the Input/output node and are subjected to power supply failure resulting in a collapsing supply voltage decaying to zero volts while said Input/output circuit has a high voltage remaining applied to its Input/output node. The Input/output buffer bias circuit is comprised of a sensing circuit and a bias generator circuit which acts to drive protection transistors in a manner which optimally minimizes the voltage impressed on input or output devices under all conditions which could persist in the event of VDD supply voltage failure. Protection circuitry holds all three combinations of voltage stress, gate-to-source, gate-to-drain, and drain-to-source voltages, to acceptable levels.

Abstract: A test circuit (10) is provided to enable testing for faults in internal cascode transistors Q2 and Q3, which form part of, for example, a level shifting circuit. Test circuit (10) is comprised of test transistors Q6 and Q7 connected to regulating transistors Q5 and Q8. When Q2 and Q3 are functioning properly, no current flow through test circuit (10). If, however, either or both of Q2 or Q3 has a drain to source short, current flows through test circuit (10) thus providing an indication of the fault.

Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) having a gate oxide protected from voltage changes on an output (16). A second output driver (88) also has a gate oxide protected from voltage changes on the output (16). A level shifter (60) includes at least one cascode device (66, 68, 70, 72) and switches the first output driver (86) according to the values of a data input (12) and an enable input (14). A bias-generation circuit (300) generates a quasi-failsafe voltage that is approximately equal to a chip core voltage when a power supply (4) is supplying the chip core voltage and equal to a portion of the chip core voltage when the power supply (4) is not supplying the chip core voltage. The bias-generation circuit (300) is coupled to a first output cascode (80) coupled to the first output driver (86), to a second output cascode (84) coupled to the second output driver (88), or to the cascode device (66, 68, 70, 72) of the level shifter (60).