Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) and a second output driver (88). A first output cascode (80) coupled to the first output driver (86) protects the gate oxide of the first output driver (86) from voltage changes on the output (16). A second output cascode (84) coupled to the second output driver (88) protects the gate oxide of the second output driver (88) from voltage changes on the output (16). A level shifter (60) includes multiple cascode devices (66, 68, 70, 72) and switches the first output driver according to the values of a data input (12) and an enable input (14). A first testability device (202, 204, 206, 208) coupled to a cascode device (66, 68, 70, 72) of the level shifter (60) generates a current in response to failure of the cascode device (66, 68, 70, 72).

Abstract: A gate array base cell (100) performs logic and memory cell functions and comprises a first P-channel transistor (M1) for performing logic functions and having a first predetermined transconductance area and a second P-channel transistor (M5) for performing memory cell functions and having a second predetermined transconductance area. The second transconductance area is smaller than said first predetermined transconductance area. The gate array base cell (100) has programmable connections to first P-channel transistor (M1) and second P-channel transistor (M5) for selectively performing memory cell functions and logic functions. The gate array base cell (100) may be connected to operate as a memory cell with logic functions or separately as a memory cell or a logic gate array, such as a two-input NAND gate (128).

Abstract: Current sensing circuits especially adapted for use with either capacitive touch plate or mechanical switch keys. The circuits include a transistor whose base is connected to a constant voltage source and whose emitter-collector circuit is connected between the touch plate or switch keys and an input to a comparator. A second transistor and a capacitor are interconnected with the first transistor to provide transient surge protection. The circuits distinguish between differing values of current and activate the comparator which produces a signal indicative of the existing condition.