Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: A method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). The accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: A test device for testing inter-device connections of field programmable gate arrays (FPGAS) by using the FPGAs themselves during testing to form a shift register. Particularly, the shift register comprises flip-flops and buffers interconnected by the actual FPGA inter-device or inter-device connections under test. A control circuit generates an input test pattern which is serially input into one end of the shift register and read out of the other end. The input pattern and the output pattern are compared to determine if they match. If they match, there are no faults through the interconnections used in the shift register. The shift register also may be bidirectional such that the input and output patterns are read in and out at the same terminal.

Abstract: A method and apparatus for negotiating access to a shared resource by two independent domains. A request register is provided to each domain for receiving an ownership request signal. Request signals received from both domains are clock-synchronized and fed to a cross-coupled circuit. The cross-coupled circuit includes two blocks, each having a switch and a register for receiving a request signal. The registers are responsive to different portions of a clock cycle, e.g., rising and falling edges. The switch in each block receives a signal from one domain on one input and a signal from the output of the register in the same block on the other input. The switch of one block is controlled by the output signal of the register of the other block. The output of one of the blocks is used to control a domain switch to permit data streams from the independent domains to reach the shared resource. Each domain requests use of the shared resource by sending a request signal to its respective request register.

Abstract: A technique is provided for setting an error status bit in a first-in, first-out memory having data words with associated error bits. When a word having an associated error bit that is set to indicate an error is written into the FIFO, the write pointer is captured, and a flag is set, indicating that the FIFO has a word with an error. If a second word is written which has an error, that pointer value is captured, overwriting the current value. As the FIFO is read, the read pointers are compared with the captured write pointer. When the values are equal, and the FIFO is read, the flag is cleared, indicating that there are no more errors in the FIFO. In an exemplary case, each word in the FIFO has 8 data bits and 3 error bits. A FIFO used in implementing a UART in a modem typically includes 16 or 32 words.

Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Abstract: An improved technique for blowing conductive links with a laser provides for a wider range of acceptable laser energies. The link in an upper interconnect level is placed on a pedestal, typically formed by etching away a thin layer of the underlying dielectric on which the conductive link is formed. A link in a lower interconnect level thereby has the thickness of the dielectric overlying it reduced. This has been found to reduce the minimum laser energy required to cleanly blow the links in both levels and to reduce the effect of link orientation on the required laser energy.

Abstract: A groove is disposed in a substrate longitudinally along the outside radius of a bent integrated optical waveguide to constrain the mode of optical energy propagating therein such that the optical energy that would normally be radiated is confined to the waveguide, thereby reducing transmission loss through the bend. Further, to reduce coupling loss between an integrated optical waveguide and an optical fiber, two grooves are disposed longitudinally along either side of the integrated optical waveguide to constrain the mode of optical energy propagating in the waveguide to approximate the mode of the optical energy propagating in the optical fiber. To further reduce both bend and coupling losses, the ends of the grooves bend away from the waveguide.

Abstract: A laser or other source of radiant electromagnetic energy removes optically transparent material (e.g., LiNbO.sub.3) to form various structures. To enhance coupling the radiant energy to the optical material, a layer of an ablative absorber (e.g., a metal or organic material) can be used. Alternately, the radiant source can be initially operated above a threshold that causes removal of a surface layer of the optical material. After selectively thus removing a surface layer of the optical material, subsequent sub-threshold applications of radiant energy remove additional optical material due to a change in the underlying material, rendering it more absorptive at the wavelength of the electromagnetic energy. Optical devices, including waveguides, can be formed, as well as isolation grooves, alignment structures, etc.