Abstract: A sensor system includes: a housing having an internal wall defining an opening; a transparent window mounted within the opening; a sensor device within the housing and having at least one of a sensor output or a sensor input alignable with the transparent window; a vibration device in communication with the transparent window, where the vibration device is controllable to produce a first sonic movement; where the transparent window is movably responsive to the first sonic movement with a second sonic movement; and at least one damping member located between the transparent window and the sensor device, where the damping member substantially isolates the sensor device from at least the second sonic movement of the transparent window. A method includes determining a cleaning trigger corresponding to cleaning the transparent window; and controlling, in response to the cleaning trigger, a vibration frequency, amplitude, or duration of the vibration device.

Abstract: An apparatus is arranged to receive and retain a needle shield for a medicament delivery device, the apparatus comprising a body comprising a wall defining a void and an opening in a proximal end of the body, the opening arranged to allow at least a part of the needle shield to be received into, and at least partially fill, the void, and arms extending from the wall into the void, wherein the arms are configured to engage the needle shield when the needle shield is received in the void and prevent the needle shield from being withdrawn from the void through the opening in the proximal end and wherein at least one of the arms has a first angle with respect to the wall and at least one of the arms has a second angle with respect to the wall that is different to the first angle.

Abstract: A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive status information regarding the one or more failures in the embedded memory; (ii) to determine whether the memory is repairable based on the status information; (iii) when the memory is deemed repairable, to store an address corresponding to a failed memory cell of the memory; (iv) to burn the address corresponding to the failed memory cell into the fuse register using a voltage source supplied to the memory repair circuit; and (v) to verify that the address corresponding to the failed memory cell was burned into the fuse register.

Abstract: A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive status information regarding the one or more failures in the embedded memory; (ii) to determine whether the memory is repairable based on the status information; (iii) when the memory is deemed repairable, to store an address corresponding to a failed memory cell of the memory; (iv) to burn the address corresponding to the failed memory cell into the fuse register using a voltage source supplied to the memory repair circuit; and (v) to verify that the address corresponding to the failed memory cell was burned into the fuse register.

Abstract: A system for supporting a projector on a support structure relative to a projection surface includes a plurality of base members connectable with the support structure and having a position adjustable relative to the projection surface. The system also includes a base member calibration system for calibrating the base members to a predetermined position relative to the projection surface. The system also includes a plurality of foot members for supporting the projector. Each foot member has a position adjustable relative to the projector. The system further includes a projector calibration system for calibrating the projector to a predetermined position relative to the foot members. The projector calibrated to the predetermined position relative to the foot members is calibrated to the predetermined position relative to the projection surface when the foot members rest on the base members.

Abstract: An integrated circuit debugger incorporated into an integrated circuit, allowing direct access to internal points within the integrated circuit. By having direct access to internal points within the integrated circuit, the debugger is capable of faster and more accurate debugging. The debugger is able to directly access internal points of the integrated circuit which were previously inaccessible or only accessible indirectly for debugging, such as memory addresses, memory data, read/write strobes, and internal chip states. In addition, by accessing internal points of the integrated circuits directly, debugging instructions can be performed in real-time with minimal interruption to the operation of the integrated circuit.

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: A flexible memory overlaying apparatus and method stores repeatedly referenced information, e.g, common global variables, common code segments, interrupt service routines, and/or any other user or system definable information, in spare addressable circuits accessed by a memory aliasing or overlaying module. The memory aliasing module monitors (or snoops) memory access by a processor to redirect access to certain appropriate addressable circuits to provide faster access to the information than would be available in an access made from main memory. The memory overlaying apparatus and method provides an efficient context switching, e.g., during an interrupt, enables a reduction in the size of instruction code requirements, and helps avoid the occurrences of cache misses, and/or thrashing between cached pages.

Abstract: A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

Abstract: An interlocutor system and method is described that allows for at-speed testing of an embedded microcontroller at the control of an embedded digital signal processor in a system-on-a-chip architecture. The interlocutor system includes a buffer for temporarily storing test program data words output by the DSP and retrieved by the microcontroller being tested and a control circuit for controlling the microcontroller and DSP. The microcontroller, DSP, and interlocutor system are all located on a single integrated circuit.

Abstract: A modem having an interactive clearing circuit that provides the facility for the modem to mix interleaved and non-interleaved writes to a FIFO without timing problems or data transfer problems associated with the prior art. The circuit includes a self-clearing error bit circuit that clears the error bits of an interleaved write from the LSR after each FIFO write. In one embodiment, the clearing circuit provides dummy bits to the LSR upon each controller write to the FIFO. This prevents error bits associated with previous interleaved writes from becoming associated with subsequent non-interleaved writes.

Abstract: An adaptive addressable circuit redundancy method and apparatus, e.g., an adaptive memory redundancy method and apparatus, utilizes an on-chip processor to test, analyze and reassign spare addressable circuits to replace defective or intermittent addressable circuits. The present invention is applicable both in a manufacturing environment and/or in a field environment wherein the integrated circuit is operational. An adaptive addressable circuit redundancy module intercepts a data path between the on-chip processor and the addressable circuits to reassign defective addresses as necessary to utilize a spare addressable circuit bank. In another embodiment of the present invention, a broadcast write module cuts memory test time almost in half by writing a same data pattern to a significant portion or all of the addressable circuits, e.g., memory, substantially simultaneously.

Abstract: A protective safety shoe insert includes a seamless puncture-resistant insole substantially conforming in shape to a sole of the shoe. The insole comprises a flexible steel plate coinciding with an area of greatest flexure of the insole and a layer of a puncture-resistant material secured to the ends of the plate. The insole is injection molded with an integral safety toe, an integral arch support, and an optional integral heel protector. A metatarsal guard is secured to the safety toe to add impact protection for the metatarsal area of the foot.

Abstract: An adaptive addressable circuit redundancy method and apparatus, e.g., an adaptive memory redundancy method and apparatus, utilizes an on-chip processor to test, analyze and reassign spare addressable circuits to replace defective or intermittent addressable circuits. The present invention is applicable both in a manufacturing environment and/or in a field environment wherein the integrated circuit is operational. An adaptive addressable circuit redundancy module intercepts a data path between the on-chip processor and the addressable circuits to reassign defective addresses as necessary to utilize a spare addressable circuit bank. In another embodiment of the present invention, a broadcast write module cuts memory test time almost in half by writing a same data pattern to a significant portion or all of the addressable circuits, e.g., memory, substantially simultaneously.

Abstract: A downhill ski boot assembly combines a flexible walking boot with a boot brace insertable into a standard ski binding to provide a skier with the control and feel of a conventional hard ski boot. The boot brace has a sole plate insertable into the ski binding, a toe cap and boot restraining means for urging the sole of the boot against the sole plate. Lower leg support is provided by the brace by means of upright supports which are preferably inner and outer lateral struts extending from the sole plate to a shin or calf piece. The lower leg support has a spring biased pivot adjacent the ankle region which allows the skier to move his lower leg forward from the ankle against a biasing force.

Abstract: A downhill ski boot assembly combines a flexible walking boot with a boot brace insertable into a standard ski binding to provide a skier with the control and feel of a conventional hard ski boot. The boot brace has a sole plate insertable into the ski binding, and toe and heel hold down structures for the flexible boot are attached to the sole plate. Lower leg support is provided by the brace by means of upright supports which are preferably inner and outer lateral struts extending from the sole plate to a shin piece. The lower leg support has a spring biased pivot adjacent the ankle region which allows the skier to move his lower leg forward from the ankle against a biasing force.

Abstract: A downhill ski boot assembly utilizes a ski boot shell into which a soft walking boot may be inserted. The shell has a rigid sole plate with a stiff forefoot and shin piece as well as heel hold down means. The forefoot and shin piece has an opening at the toe so that the boot toe may extend therethrough. The heel hold down means of the shell coacts with means on the heel of the boot to hold it in place against the sole plate. A calf strap and an instep strap provide further immobilization of the skier's leg and foot to provide the desired degree of skiing control.