Abstract: A method and circuit arrangement process a workload in a multithreaded processor that includes a plurality of hardware threads. Each thread receives at least one message carrying data to process the workload through a respective inbox from among a plurality of inboxes. A plurality of messages are received at a first inbox among the plurality of inboxes, wherein the first inbox is associated with a first thread among the plurality of hardware threads, and wherein each message is associated with a priority. From the plurality of received messages, a first message is selected to process in the first thread based on that first message being associated with the highest priority among the received messages. A second message is selected to process in the first thread based on that second message being associated with the earliest time stamp among the received messages and in response to processing the first message.

Abstract: A method and circuit arrangement process a workload in a multithreaded processor that includes a plurality of hardware threads. Each thread receives at least one message carrying data to process the workload through a respective inbox from among a plurality of inboxes. A plurality of messages are received at a first inbox among the plurality of inboxes, wherein the first inbox is associated with a first thread among the plurality of hardware threads, and wherein each message is associated with a priority. From the plurality of received messages, a first message is selected to process in the first thread based on that first message being associated with the highest priority among the received messages. A second message is selected to process in the first thread based on that second message being associated with the earliest time stamp among the received messages and in response to processing the first message.

Abstract: In a first aspect, a stream of data is transmitted by dividing the stream of data into a first substream and a second substream, transmitting the first substream in a first data channel, and transmitting the second substream in a second data channel. Before transmitting the first and second substreams, a first marker signal is inserted in the first substream and/or a second marker signal is inserted in the second substream. A receiver circuit receives the substreams, detects at least one marker signal, and reassembles the data stream from the substreams based on at least one detected marker signal. Numerous other aspects are provided.

Abstract: A method of deskewing parallel data streams includes receiving the plurality of data streams and storing each of the received data streams in a respective buffer. Synchronization signals in the data streams are detected, and the buffers are controlled to read out the stored data streams on the basis of the detected synchronization signals. Numerous other methods and apparatus are provided.

Abstract: In a first aspect, a stream of data is transmitted by dividing the stream of data into a first substream and a second substream, transmitting the first substream in a first data channel, and transmitting the second substream in a second data channel. Before transmitting the first and second substreams, a first marker signal is inserted in the first substream and/or a second marker signal is inserted in the second substream. A receiver circuit receives the substreams, detects at least one marker signal, and reassembles the data stream from the substreams based on at least one detected marker signal. Numerous other aspects are provided.

Abstract: A method and apparatus for reducing bipolar current effects in dynamic logic circuits that are fabricated using the SOI technology is disclosed. A dynamic logic circuit capable of reducing bipolar current effects includes a precharge transistor (or a discharge transistor), a pass transistor, a functional logic circuit block, and an inverter. Connected in series with the precharge transistor, the functional logic circuit block, which includes multiple transistors, receives signal inputs. The pass transistor, connected in parallel with the precharge transistor, receives an identical input as one of the many transistors within the functional logic circuit block. The inverter, connected to a node between the precharge transistor and the functional logic circuit block, provides an output for the dynamic logic circuit.

Abstract: A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.

Abstract: A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.