Abstract: A guide probe test system for isolating faults in PC boards performs a "variable time domain" analysis by comparing probed data with stored reference data of waveforms of a known good UUT (unit under test) that are augmented by (1) insertion of shift coefficients to compensate for non-synchronization of the probed data with a start event, and (2) insertion of jitter coefficients to compensate for timing variations in the probed data due to allowable component propagation delay tolerances and/or an asynchronous clock. The insertion of the shift and jitter coefficients creates failure ranges within which mismatches of the probed data with the reference data are treated as possible rather than absolute failures. The UUT is partitioned into measurement sets containing nodes with common stimulus and synchronization to allow the analysis to break feedback loops and isolate faulty components.