Abstract: A logical data block in a MRAM is disclosed. The logical data block comprises magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor. The logical data block may further be configured in size by a preselected, block-based error correction code. A magnetic memory module and computer system including a MRAM having a logical data block according to embodiments of the present invention are also disclosed. Additionally, a method embodiment of reducing half-select write errors within a MRAM is disclosed.

Abstract: Imaging methods, image sensors, imaging systems, and articles of manufacture are described. According to one embodiment, an imaging method provides providing an image sensor, receiving light using the image sensor, using the image sensor, providing image data of an image according to a first coordinate space responsive to the receiving, transforming at least a portion of the image data from the first coordinate space to a second coordinate space different than the first coordinate space, and displaying at least a portion of the image using the image data according of the second coordinate space.

Abstract: An iris feature detector includes a reflexive eye movement source; a multiple image sensor; a controller, and a processor. The controller causes the eye movement source to cause rapid eye motion, and the sensor to capture first and second iris images over a time interval in which only an iris can move in the first and second images. The processor determines differences between the first and second images. The sensor may be integrated with the processor. The integrated sensor/processor is not limited to iris feature detection, and may be used for edge detection for machine vision and other applications.

Abstract: An embodiment includes a resistance change sensor. The resistance change sensor includes a first input connected to a first resistance and a second input connected to a second resistance.

Abstract: A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.

Abstract: A logical data block in a MRAM is disclosed. The logical data block comprises magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor. The logical data block may further be configured in size by a preselected, block-based error correction code. A magnetic memory module and computer system including a MRAM having a logical data block according to embodiments of the present invention are also disclosed. Additionally, a method embodiment of reducing half-select write errors within a MRAM is disclosed.