Patents by Inventor Frederick Rodriguez Dahilig

Frederick Rodriguez Dahilig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8937393
    Abstract: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig
  • Patent number: 8810015
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: August 19, 2014
    Assignee: STAT ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig
  • Patent number: 8405230
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 26, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Marie L. Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Rodriguez Dahilig
  • Patent number: 8344495
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the substrate external layer; forming an insulation layer over the substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect; and connecting an integrated circuit and the horizontal conductive pathway.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: January 1, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Philip Lyndon Cablao, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig
  • Publication number: 20120241968
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig, Jairus Legaspi Pisigan
  • Patent number: 8174127
    Abstract: A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: May 8, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, Jr., Dioscoro A. Merilo
  • Patent number: 8120187
    Abstract: A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, Jr., Dioscoro A. Merilo
  • Publication number: 20110298113
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8022539
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: September 20, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20110147899
    Abstract: A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.
    Type: Application
    Filed: March 3, 2011
    Publication date: June 23, 2011
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, JR., Dioscoro A. Merilo
  • Publication number: 20110140261
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the substrate external layer; forming an insulation layer over the substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect; and connecting an integrated circuit and the horizontal conductive pathway.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Inventors: Zigmund Ramirez Camacho, Philip Lyndon Cablao, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig
  • Publication number: 20110012270
    Abstract: A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 20, 2011
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, JR., Dioscoro A. Merilo
  • Publication number: 20100320591
    Abstract: A method of manufacture of an integrated circuit packaging system includes: attaching contact pads to a base structure; connecting a base die to the base structure; connecting a supporting die over the base die by conductive balls to the contact pads on two sides of the base die; encapsulating the contact pads, the base die, the supporting die, and the conductive balls; and removing the base structure.
    Type: Application
    Filed: June 19, 2009
    Publication date: December 23, 2010
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Frederick Rodriguez Dahilig
  • Publication number: 20100314731
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig
  • Patent number: 7830020
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 9, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, Jr., Dioscoro A. Merilo
  • Publication number: 20100123230
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first terminal having a cavity; mounting a first integrated circuit over the first terminal and connected in the cavity; forming a second terminal adjacent to the first terminal; connecting a second integrated circuit, over the first integrated circuit, and the second terminal; and forming a first encapsulation over the first integrated circuit with the first terminal exposed.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20100123227
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, includes having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.
    Type: Application
    Filed: November 17, 2008
    Publication date: May 20, 2010
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20080315411
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, JR., Dioscoro A. Merilo
  • Publication number: 20080272479
    Abstract: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 6, 2008
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig