Abstract: A computer readable medium embodies a set of instructions. The set of instructions includes an instruction to manipulate a processor to determine a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component. The instruction further is to transfer a data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.

Abstract: There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an input and an output, wherein the data latch comprises a) a first inverter having an input coupled to the first I/O line and an output coupled to the second I/O line, and b) a second inverter having an input coupled to the second I/O line and an output coupled to the first I/O line. The storage cell also comprises a biasing circuit that forces at least one of the first and second I/O lines to a known logic state when power is applied to the SRAM device. The known logic state comprises one bit in the embedded program.

Abstract: There is disclosed a data processor having improved debugging features that output from the data processor selected instructions, data, or addresses in response to the occurrence of one or more of events in the data processor. The events include execution of a branch instruction, detection of a trigger value on an internal bus, or execution of a unique spray instruction.

Abstract: A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.

Abstract: A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated addresses. A first preferred embodiment employs two signals namely: translation request and translation address strobe to request/acknowledge the request for translation. The translation request is maintained asserted by one of the alternative bus masters until the central processor acknowledges it--at which time the alternative bus master drives an address (for example a virtual address) onto the address bus for translation. The central processor then translates the virtual address to its corresponding physical address (doing any page table walking or page faulting) and drives this physical address out on the address lines and asserts another translation address strobe.

Abstract: A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.

Abstract: A processing system removes the burden of maintaining legacy hardware by employing a system management mode mechanism to provide an environment for virtualizing preexisting memory and I/O space instructions into operations for high resolution raster graphics circuitry, thus maintaining functionality and backwards compatibility with preexisting software.