Abstract: A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.

Abstract: An integrated circuit bipolar bootstrap driver has an interface circuit means, a low logic level circuit means and a bootstrap, high logic level circuit means. The interface circuit means is coupled to the low logic level and high logic level circuit means and selectively activates one of the circuit means in response to an input signal. The high logic level circuit means includes an integrated circuit npn Darlington pair and a pnp low current, low speed lateral type integrated circuit transistor in combination with an integrated circuit capacitor which is used to provide a bootstrapped high logic level signal.

Abstract: A bipolar random access memory cell is disclosed using a pair of transistors cross-coupled in a flip flop configuration with the transistors connected to operate in the inverted mode, that is, the collectors as emitters and the emitters as collectors. This allows an integrated circuit realization of a random access memory having only one and one-half isolation regions per row of memory cells. Forming the flip flop load resistors by the emitter-pinched base method compensates the cell for process variations to result in substantially constant read/write characteristics.