Patents by Inventor Frederick Vratny

Frederick Vratny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4822754
    Abstract: A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.
    Type: Grant
    Filed: June 12, 1984
    Date of Patent: April 18, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: William T. Lynch, Frederick Vratny
  • Patent number: 4496448
    Abstract: A method and apparatus for fabricating a device is disclosed, which method involves a new reactive ion etching technique. Both a high etch rate and, for example, a high etch selectivity are simultaneously achieved with the inventive reactive ion etching technique by discharging an electrode of the reactive ion etching apparatus in response to a preselected criterion, e.g., a magnitude of a DC bias at said electrode which equals, or exceeds, a preselected value.
    Type: Grant
    Filed: October 13, 1983
    Date of Patent: January 29, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: King L. Tai, Frederick Vratny
  • Patent number: 4481251
    Abstract: A polyarylate polymer is deposited on a substrate in accordance with a fabrication procedure that ensures an adherent low-stress conformal coating. Such a coating is advantageous for use in a number of industrial applications of practical importance.
    Type: Grant
    Filed: April 27, 1983
    Date of Patent: November 6, 1984
    Assignee: AT&T Bell Laboratories
    Inventor: Frederick Vratny
  • Patent number: 4453306
    Abstract: A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.
    Type: Grant
    Filed: May 27, 1983
    Date of Patent: June 12, 1984
    Assignee: AT&T Bell Laboratories
    Inventors: William T. Lynch, Frederick Vratny
  • Patent number: 4427516
    Abstract: In a plasma-assisted etching apparatus and method designed to pattern silicon dioxide in a plasma derived from a mixture of trifluoromethane and ammonia, surfaces in the reaction chamber are coated with a layer of silicon. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.
    Type: Grant
    Filed: March 4, 1983
    Date of Patent: January 24, 1984
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Hyman J. Levinstein, Frederick Vratny
  • Patent number: 4419201
    Abstract: In a plasma-assisted etching apparatus and method designed to pattern aluminum or polysilicon, surfaces in the reaction chamber are coated with a layer of aluminum oxide. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: December 6, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Hyman J. Levinstein, Frederick Vratny
  • Patent number: 4362597
    Abstract: It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.
    Type: Grant
    Filed: January 19, 1981
    Date of Patent: December 7, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: David B. Fraser, Eliezer Kinsbron, Frederick Vratny
  • Patent number: 4346125
    Abstract: In an integrated circuit fabrication sequence, a hardened mask pattern adhered to an underlying substrate is removed from the substrate by a solvent that comprises anhydrous hydrazine and dimethyl sulfoxide. The solvent rapidly penetrates the interface between the pattern and the underlying substrate and quickly breaks the adhesive bonds therebetween. Other materials (e.g., Al, Si, SiO.sub.2) in the structure being fabricated are not deleteriously affected by the solvent.
    Type: Grant
    Filed: December 8, 1980
    Date of Patent: August 24, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Eliezer Kinsbron, Frederick Vratny
  • Patent number: 4319967
    Abstract: A fabrication process for making palladium-plated target anodes for X-ray lithographic systems is characterized by a unique sequence of surface preparation, plating and annealing steps. Anodes made by the process have been operated reliably at high-power levels for extended periods of time.
    Type: Grant
    Filed: November 1, 1979
    Date of Patent: March 16, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Frederick Vratny, John M. Andrews, Jr.
  • Patent number: 4238682
    Abstract: Even ultra-thin films deposited on the surface of a high-power X-ray target anode (14) during water cooling thereof form thermal barriers that significantly limit the lifetime of the anode. The deposition of such films on the anode is minimized by utilizing several techniques. These include the use of low-corrosion metals such as high-chrome stainless steel in the cooling system, preferential etching of the water-carrying metallic members to provide chrome-rich surfaces, and complexing the metallic hydroxides that are produced in the cooling medium to hold them in a highly soluble state even in the immediate vicinity of the hot anode. These techniques, coupled with submicron filtering and systematic cleaning and maintenance of the cooling system, are important contributors to achieving highly reliable long-lifetime operation of a high-power X-ray source.
    Type: Grant
    Filed: May 3, 1979
    Date of Patent: December 9, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Frederick Vratny
  • Patent number: 4154877
    Abstract: A method for depositing electroless nickel on aluminum or aluminum alloy is described. The method is particularly useful for fabricating bonding pads on aluminum metallized semiconductor devices and for creating beam leads. The described method deposits a thick nickel layer directly on aluminum without the use of intermediate layers or surface activation as required in the prior art. The method basically comprises immersion in a stop-etchant which simultaneously removes aluminum oxide and activates the surface; immersion in a solution which activates the aluminum with nickel ions and deactivates mask material; and immersion in a novel electroless nickel bath. A technique for electrolessly depositing gold is also described.
    Type: Grant
    Filed: April 14, 1978
    Date of Patent: May 15, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Frederick Vratny
  • Patent number: 4125648
    Abstract: A method for depositing electroless nickel on aluminum or aluminum alloy is described. The method is particularly useful for fabricating bonding pads on aluminum metallized semiconductor devices and for creating beam leads. The described method deposits a thick nickel layer directly on aluminum without the use of intermediate layers or surface activation as required in the prior art. The method basically comprises immersion in a stop-etchant which simultaneously removes aluminum oxide and activates the surface; immersion in a solution which activates the aluminum with nickel ions and deactivates mask material; and immersion in a novel electroless nickel bath. A technique for electrolessly depositing gold is also described.
    Type: Grant
    Filed: April 14, 1978
    Date of Patent: November 14, 1978
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Frederick Vratny
  • Patent number: 4122215
    Abstract: A method for depositing electroless nickel on aluminum or aluminum alloy is described. The method is particularly useful for fabricating bonding pads on aluminum metallized semiconductor devices and for creating beam leads. The described method deposits a thick nickel layer directly on aluminum without the use of intermediate layers or surface activation as required in the prior art. The method basically comprises immersion in a stop-etchant which simultaneously removes aluminum oxide and activates the surface; immersion in a solution which activates the aluminum with nickel ions and deactivates mask material; and immersion in a novel electroless nickel bath. A technique for electrolessly depositing gold is also described.
    Type: Grant
    Filed: December 27, 1976
    Date of Patent: October 24, 1978
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Frederick Vratny
  • Patent number: H13
    Abstract: A unique socket assembly is designed to interconnect a flat-pack-packaged integrated-circuit chip to a printed-circuit board in a manner that permits easy insertion and withdrawal of the packaged chip from the assembly. A base portion of the assembly includes a recess into which conductive cantilevered elements extend. When the packaged chip is positioned on these elements within the recess and a lid is placed on the base, secure but not permanent electrical contact is established between the elements and contact regions on the chip package.
    Type: Grant
    Filed: August 13, 1984
    Date of Patent: January 7, 1986
    Assignee: AT&T Bell Laboratories
    Inventor: Frederick Vratny