Abstract: Multiply-accumulate processors within a tensor processing unit simultaneously execute, in each of a sequence of multiply-accumulate cycles, respective multiply operations using a shared input data operand and respective weighting operands, each of the multiply-accumulate processors applying a new shared input data operand and respective weighting operand in each successive multiply-accumulate cycle to accumulate, as a component of an output tensor, a respective sum-of-multiplication-products.

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N?1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

Abstract: An integrated circuit including memory to store image data and filter weights, and a plurality of multiply-accumulator execution pipelines, each multiply-accumulator execution pipeline coupled to the memory to receive (i) image data and (ii) filter weights, wherein each multiply-accumulator execution pipeline processes the image data, using associated filter weights, via a plurality of multiply and accumulate operations. In one embodiment, the multiply-accumulator circuitry of each multiply-accumulator execution pipeline, in operation, receives a different set of image data, each set including a plurality of image data, and, using filter weights associated with the received set of image data, processes the set of image data associated therewith, via performing a plurality of multiply and accumulate operations concurrently with the multiply-accumulator circuitry of the other multiply-accumulator execution pipelines, to generate output data.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain.

Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract: An integrated circuit including a multiplier-accumulator execution pipeline including a plurality of multiplier-accumulator circuits to, in operation, perform multiply and accumulate operations, wherein each multiplier-accumulator circuit includes: (i) a multiplier to multiply first input data, having a first floating point data format, by a filter weight data, having the first floating point data format, and generate and output a product data having a second floating point data format, and (ii) an accumulator, coupled to the multiplier of the associated MAC circuit, to add second input data and the product data output by the associated multiplier to generate sum data. The plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline may be connected in series and, in operation, perform a plurality of concatenated multiply and accumulate operations.

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio.