Abstract: An adapter layer may be used to customize a machine learning component by transforming data flowing into, out of, and/or within the machine learning component. The adapter layer may include a number of neural network components, or “adapters,” configured to perform a transformation on input data. Neural network components may be configured into adapter groups. A router component can, based on the input data, select one or more neural network components for transforming the input data. The input layer may combine the results of any such transformations to yield adapted data. Different adapter groups can include adapters of different complexity (e.g., involving different amounts of computation and/or latency). Thus, the amount of computation or latency added by an adapter layer can be reduced for simpler transformations of the input data.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: The present invention provides a method of inducing an immune response against Campylobacter in an avian species, especially a domesticated avian species such as chicken, turkey, duck, goose and quail, by administering, in ovo, live cells of Campylobacter.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, at least one of the memory modules includes a cache for storing data stored in a system memory.

Abstract: A system includes a host coupled to a serially connected chain of memory modules. In one embodiment, the host includes a memory controller that may be configured to issue a memory read request for data stored within the memory modules. The memory controller may further request that data be prefetched from the memory modules by encoding prefetch information within the memory read request. The memory controller may also be configured to issue a memory write request to write data to the memory modules and to selectively request that one or more pages of memory within a given one of the memory modules remain open by encoding the prefetch information within the memory write request.

Abstract: A method for routing clock signals in an integrated circuit provides a hierarchical routing scheme in which the lowest level clock buffers are first placed row by row in preallocated locations and routed to the input pins of standard cells receiving the output clock signals of these clock buffers. Under the method, the number of clock buffers to be placed in each row is computed according to estimates of their load capacitances and expected wiring lengths within a window. The output buffers of the same clock signal are gridded or strapped together to minimize clock skew. A second level of clock buffers are then assigned to drive the lowest level buffers. The hierarchy can be extended to any number of higher levels, until clock signals are routed for the entire integrated circuit. The higher level clock signals can also be strapped or gridded to minimize clock skew.

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: A method for routing clock signals in an integrated circuit provides a hierarchical routing scheme in which the lowest level clock buffers are first placed row by row in preallocated locations and routed to the input pins of standard cells receiving the output clock signals of these clock buffers. Under the method, the number of clock buffers to be placed in each row is computed according to estimates of their load capacitances and expected wiring lengths within a window. The output buffers of the same clock signal are gridded or strapped together to minimize clock skew. A second level of clock buffers are then assigned to drive the lowest level buffers. The hierarchy can be extended to any number of higher levels, until clock signals are routed for the entire integrated circuit. The higher level clock signals can also be strapped or gridded to minimize clock skew.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.